Advanced Micro Devices Corporation

Globalfoundries Inc.

Stephen G Beebe

Akram Ali Salman

Zoran Krivokapic

Srinath Krishnan

Shuqing Cao

Kurt Taylor

Wensong Chen

Xuejun Zhao

Apparatus are provided for integrated circuits that include circuitry to provide protection from electrostatic discharge. An exemplary integrated circuit includes an input/output terminal, a first transistor coupled to the input/output terminal, a second transistor coupled to a control terminal of the first transistor and a reference voltage node, and detection circuitry coupled to a control terminal of the second transistor. The detection circuitry is configured to turn on the second transistor in response to a discharge event to protect the first transistor.

Integrated circuit having electrostatic discharge protection

An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers () in a first well region () that is disposed between anode and cathode regions () in response to one or more bias voltages (GG) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Field effect resistor for ESD protection

An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers () in a first well region () that is disposed between anode and cathode regions () in response to one or more bias voltages (G, G) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second portion of the silicon substrate to define a first conductivity-type diode region within the silicon substrate. Ions of a second conductivity-type are implanted into a third portion of the silicon substrate to define a second conductivity-type diode region within the silicon substrate. During one of the steps of implanting ions of the first conductivity-type and implanting ions of the second conductivity-type, ions are also implanted into at least part of the first portion to define a separation region within the first portion. The separation region splits the first portion into a first well device region and a second well device region. The separation region is formed in series between the first well device region and the second well device region.

Electrostatic discharge protection devices

Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.

Electrostatic discharge protection devices and methods for protecting semiconductor devices against electrostatic discharge events

An electrostatic discharge (ESD) protection circuit and a method for reducing capacitance in the ESD protection circuit. A pair of gated diodes are connected in series, wherein the anode of one of the gated diodes is coupled to a lower voltage supply node and the cathode the other gated diode is connected to the upper voltage supply node. The commonly connected anode and cathode of the series connected gated diodes are connected to an input/output pad and to receiver and driver circuitry. The gates of the gated diodes are connected together. A gate biasing circuit is connected to the gates of the gated diodes. The gate biasing circuit applies a voltage to the gates of the gated diodes and depletes their channel regions of charge carriers, which lowers the capacitances of each gate diode.

ESD protection circuit and method for lowering capacitance of the ESD protection circuit

An electrostatic discharge ('ESD') protection circuit having dynamically configurable series-connected diodes and a method for manufacturing the ESD protection circuit. A doped region of P-type conductivity and a doped region of N-type conductivity are formed in an SOI layer of P-type conductivity, wherein the doped regions are laterally spaced apart by a portion of the SOI layer. At least one gate structure is formed on the SOI region that is between the N-type and P-type doped regions. During normal operation, a portion of the SOI region that is adjacent to and between the P-type and N-type doped regions is biased so that it becomes a region of N-type conductivity, thereby forming two series-connected diodes. During an ESD event, the bias is changed so that the region between the P-type and N-type doped regions becomes a region of P-type conductivity, thereby forming a single P-N junction diode.

Protection element and method of manufacture

The present invention is generally directed to various methods for determining the reliability of dielectric layers. In one illustrative embodiment, the method comprises providing a device having a dielectric layer, applying a plurality of constant voltage pulses to the device and measuring a current through the dielectric layer after one or more of the constant voltage pulses has been applied.

Method for determining the reliability of dielectric layers

A semiconductor component having a tuned variable resistance resistor and a method for manufacturing the tuned variable resistance resistor. A semiconductor process for manufacturing a semiconductor component is selected. For the selected process, the tuned variable resistance resistor is characterized to determine the maximum stress current as a function of the width of the tuned variable resistance resistor. Then, for a given width and maximum stress current, the voltages across the resistors are characterized as a function of length. A tuned variable resistance resistor having a length and width capable of sustaining a predetermined maximum stress current is integrated into a semiconductor component. The semiconductor component may include protection circuitry designed in accordance with the Human Body Model, the Charge Device Model, or both.

Semiconductor component and method of manufacture

An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug

An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a filled backside contact opening disposed under and in thermal contact with at least one of the anode or the cathode, the backside contact opening traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

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Mountain View, CA, United States of America

Stephen G Beebe