Microsoft Technology Licensing, LLC

Stephen Francis Heil

Douglas Christopher Burger

Andrew Richard Putnam

Sitaram V Lanka

Eric S Chung

Adrian Michael Caulfield

Yi Xiao

Eric Clarence Peterson

Antony Ian Taylor Rowstron

Austin N Donnelly

Adam B Glass

Michael David Haselman

David Alex Butler

Sergey Legtchenko

Shobana Balakrishnan

David T Harper

Aaron L Smith

Suyash Sinha

David Tennyson Harper, Iii

Ajith Jayamohan

Alexey Pakhunov

Shobana M Balakrsihnan

A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

Data processing system having a hardware acceleration plane and a software plane

Aspects extend to methods, systems, and computer program products for allocating acceleration component functionality for supporting services. A service manager uses a finite number of acceleration components to accelerate services. Acceleration components can be allocated in a manner that balances load in a hardware acceleration plane, minimizes role switching, and adapts to demand changes. When role switching is appropriate, less extensive mechanisms (e.g., based on configuration data versus image files) can be used to switch roles to the extent possible.

Allocating acceleration component functionality for supporting services

A hardware acceleration component is provided that includes a plurality of hardware clusters, each hardware cluster comprising a plurality of soft processor cores and a functional circuit. The plurality of soft processor cores share the functional circuit.

Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit

Dynamic power routing is utilized to route power from other components, which are transitioned to lower power consuming states, in order to accommodate more efficient processing of computational tasks by hardware accelerators, thereby staying within electrical power thresholds that would otherwise not have accommodated simultaneous full-power operation of the other components and such hardware accelerators. Once a portion of a workflow is being processed by hardware accelerators, the workflow, or the hardware accelerators, can be self-throttling to stay within power thresholds, or they can be throttled by independent coordinators, including device-centric and system-wide coordinators. Additionally, predictive mechanisms can be utilized to obtain available power in advance, by proactively transitioning other components to reduced power consuming states, or reactive mechanisms can be utilized to only transition components to reduced power consuming states when a specific need for increased hardware accelerator power is identified.

Dynamic power routing to hardware accelerators

Aspects extend to methods, systems, and computer program products for changing between different roles at acceleration components. Changing roles at an acceleration component can be facilitated without loading an image file to configure or partially reconfigure the acceleration component. At configuration time, an acceleration component can be configured with a framework and a plurality of selectable roles. The framework also provides a mechanism for loading different selectable roles for execution at the acceleration component (e.g., the framework can include a superset of instructions for providing any of a plurality of different roles). The framework can receive requests for specified roles from other components and switch to a subset of instructions for the specified roles. Switching between subsets of instructions at an acceleration component is a lower overhead operation relative to reconfiguring or partially reconfiguring an acceleration component by loading an image file.

Changing between different roles at acceleration components

A data processing system is described herein that includes two or more software-driven host components that collectively provide a software plane. The data processing system further includes two or more hardware acceleration components that collectively provide a hardware acceleration plane. The hardware acceleration plane implements one or more services, including at least one multi-component service. The multi-component service has plural parts, and is implemented on a collection of two or more hardware acceleration components, where each hardware acceleration component in the collection implements a corresponding part of the multi-component service. Each hardware acceleration component in the collection is configured to interact with other hardware acceleration components in the collection without involvement from any host component. A function parsing component is also described herein that determines a manner of parsing a function into the plural parts of the multi-component service.

Implementing a multi-component service using plural hardware acceleration components

Aspects extend to methods, systems, and computer program products for locally restoring functionality at acceleration components. A role can be locally restored at an acceleration component when an error is self-detected at the acceleration component (e.g., by local monitoring logic). Locally restoring a role can include resetting internal state (application logic) of the acceleration component providing the role. Self-detection of errors and local restoration of a role is less resource intensive and more efficient than using external components (e.g., high-level services) to restore functionality at an acceleration component and/or to reset an entire graph. Monitoring logic at multiple acceleration components can locally reset roles in parallel to restore legitimate behavior of a graph.

Locally restoring functionality at acceleration components

Low cost storage for write once read rarely data is described. In an embodiment a storage device comprises a plurality of hard disk drives connected to a server via an interconnect fabric. The storage device comprises a cooling system which is only capable of cooling a first subset of the hard disk drives and a power supply system which is only capable of powering a second subset of the hard disk drives and in some examples, the interconnect fabric may be only capable of providing full bandwidth for a third subset of the hard disk drives. Each subset may comprise only a small fraction of hard disk drives. A control mechanism, which may be implemented in software, is provided which controls which hard disk drives are active at any time in order that the constraints set by the cooling and power supply systems and interconnect fabric are not violated.

Low cost storage for rarely read data

Aspects extend to methods, systems, and computer program products for reassigning service functionality between acceleration components. Reassigning service functionality can be used to recover service acceleration for a service. Service acceleration can operate improperly due to performance degradation at an acceleration component. A role at the acceleration component having degraded performance can be assigned to another acceleration component to restore service acceleration for the service.

Restoring service acceleration

A subject disclosure is directed towards emulating a data network interface for operating an interconnect controller in accordance with a networking standard. The emulated data network interface provides address resolution data associated with a destination, within a converged interconnect fabric, for application data. The address resolution data identifies a communication path that is compatible with the interconnect controller. The application data conforms to the networking standard. The emulated data network interface instructs the interconnect controller to route the application data to the destination via the compatible communication path.

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Sammamish, WA, United States of America

Stephen Francis Heil