Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Sanblaze Technology, Inc.

Stephen F Shirron

Frederick G Kleinsorge

Karen Lee Noel

Arthur James Beaverson

Andrew Halstead Mason

James R Kauffman

Paul Karl Harter, Jr

Gregory H Jordan

Kevin R Peterson

Thomas E Hunt

Stephen H Zalewski

B Vincent Asbridge

Harold Canute Buckingham, Iii

Ralph O Weber

Marco Ciaffi

Fidelma Hayes

Rachael Berman

PCIe devices may be connected to a test system for development, quality assurance, manufacturing, design validation, qualification, certification, and other testing. PCIe bus or other unexpected errors can avoid direct capture by the test system. Inserting a PCIe analyzer can capture a trace of PCIe bus data around any specific trigger. Due to the high volume and speed of data crossing the data bus when testing multiple devices, finding a correct trigger for an analyzer trace capture is akin to finding a needle in a haystack. By configuring a specific trigger pattern that the test system can send across the PCIe bus without impacting any of the devices under test, the test system can trigger the analyzer at the precise time needed to capture a PCIe bus data trace around the error.

System and method for testing non-volatile memory express storage devices

Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree.

Multiprocessor computer architecture with multiple operating system instances and software controlled resource allocation

Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one operating system instance to another, allowing different loads in the system to be accommodated. The migrations involve storing the processing context of a migrating processor prior to its reassignment and, after reassignment, loading any previous processing context that it may have stored from a previous execution with the partition to which it is reassigned. Hardware flags are also provided which include an identification of which CPU belongs to which partition, and an availability indicator for each CPU, which indicates whether a given CPU is available for SMP operation.

Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory space

Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one partition and operating system instance to another, allowing different loads in the system to be accommodated. The migrations may occur when the processor is executing under an operating system instance or when it is in a stopped state, and may involve the deassignment of the processor before it is reassigned to a second partition.

Method and apparatus for processor migration from different processor states in a multi-processor computer system

A memory of a computer system is sized and configured after the memory has been loaded with data. The sizing and configuration of the memory causes the data to become scattered among memory chips on a single memory module or among two or more memory modules. To gather the data, gather code loads itself into the instruction cache of the computer system and while executing from the instruction cache configures the memory and gathers the data in the memory such that it is again located at the same address it held before the configuration occurred.

Method for altering memory configuration and sizing memory modules while

An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.

Method and apparatus for fault tolerant BIOS addressing

An apparatus which allows for software sharing between multiple controllers includes a computer bus and a plurality of processors each having input and output ports coupled to the bus. Each processor also has at least one internal storage register. The apparatus further includes means, which are responsive to a signal indicating which one of the plurality of processors is controlling the computer bus and to a portion of address data on the bus, for issuing a control signal to one of the plurality of processors to permit that one processor access to at least one of its internal storage register when that processor issues a bus access request having an address which is within the range of addresses of all the processors.

Microprocessor system for selectively accessing a processor internal

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Acton, MA, United States of America

Stephen F Shirron