Advanced Micro Devices Corporation

Broadcom Corporation

Stephen F Greenwood

Bruce A Doyle

Shawn Searles

Emerson S Fang

Alvin L Loke

Scott C Savage

Christopher Michael Ward

Michael Dreesen

Josh Crohn

A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. The termination circuit includes a plurality of resistive components coupled in series with the pad and a plurality of switches. Each switch is to couple one or more of the plurality of resistive components in series between the pad and a termination voltage node when the switch is closed. A subset of the plurality of switches can be selectively closed to establish a resistive component of an impedance of the termination circuit.

Variable series resistance termination for wireline serial link transistor

A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

High efficiency voltage level multiplier

Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Shared integrated sleep mode regulator for SRAM memory

A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Clock generator with integrated phase offset programmability

An electronic circuit includes a differential input section, a current mirror section, an operational amplifier, an inverter, and a compensation voltage generator. The differential input section and the current mirror section are coupled together, forming a first common drain node and a second common drain node. The current mirror section has two p-type transistors coupled together at a common gate node. The operational amplifier has a positive input coupled to the first common drain node, a negative input coupled to the compensation voltage generator, and an output coupled to the common gate node. The inverter has an input node coupled to the second common drain node. The compensation voltage generator provides a compensation voltage to replicate a switching threshold voltage of the inverter.

Electronic comparison circuit

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

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Fort Collins, CO, United States of America

Stephen F Greenwood