International Business Machines Corporation

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Mentor Graphics Corporation

Stephen Edward Greco

Rasit Onur Topaloglu

Vincent James McGahay

Nancy Anne Greco

Theodorus E Standaert

Andrew Herbert Simon

Naftali Eliahu Lustig

Matthew S Angyal

Thomas W Dyer

Kamalesh K Srivastava

John Patrick Hummel

Rebecca D Mih

Joyce C Liu

Hua Xiang

Robert F Cook

Ronald G Filippi

Griselda Bonilla

Terry Allen Spooner

Junjing Bao

Timothy A Brunner

James A Culp

Samuel S Choi

Bernhard R Liegl

Chih-Chao Yang

Dureseti Chidambarrao

Soon-Cheon Seo

Timothy Joseph Dalton

Stephen McConnell Gates

John Anthony Fitzsimmons

Satyanarayana Venkata Nitta

Chao-Kun Hu

Paul Stephen McLaughlin

Sujatha Sankaran

Tina Jane Wagner

Lawrence Alfred Clevenger

Cyprian Emeka Uzoh

Sampath Purushothaman

Kenneth Parker Rodbell

Yun-Yu Wang

Jeffrey Curtis Hedrick

Kwong Hon Wong

Shyng-Tsong Chen

Erik L Hedberg

Klaus D Beyer

Robert Rosenberg

Habib Hichri

John M Aitken

William Harrington Brearley

Ernest N Levine

Jia Lee

Glenn A Biery

Keith Thomas Kwietniak

Billy L Crowder

Kia S Low

Eduardo Garcia

Anthony K Stamper

Yun Yu Wang

Shom Ponoth

Arne Watson Ballantine

Christopher David Muzzy

Laertis Economikos

David Lee Rath

Ruchir Puri

Edward Crandal Cooney, Iii

Norman Jay Rohrer

Carlos Juan Sambucetti

Kaushik Chanda

Kaushik Arun Kumar

Michael D Armacost

Sunfei Fang

Lee Matthew Nicholson

Kris V Srikrishnan

Ronald A Warren

Douglas Wayne Kemerer

Wei-Tsu Tseng

Xiaomeng Chen

Ronald Dean Goldblatt

Jeffrey D Gilbert

Larry Clevenger

Jean E Wynne

Andy Cowley

Henry A Bonges, Iii

Ishtiaq Ahsan

Glenn Robert Miller

Mohammed Fazil Fayaz

Ian P Stobert

George A Dunbar, Iii

Minakshisundaran Balasubramanian Anand

Patricia A O'Neil

Tze-man Ko

Frank V Liucci

Dae-Young Jung

Dennis C Green

Cheryl Faltermeier

Christine Mary Bunke

Simon M Karecki

David H Yao

Bruce A Root

Albrik Avanessian

Pegeen M Davis

A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

Multiple-depth trench interconnect technology at advanced semiconductor nodes

Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

Early overlay prediction and overlay-aware mask design

A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Interconnect level structures for confining stitch-induced via structures

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Selective local metal cap layer formation for improved electromigration behavior

Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

Stitch-derived via structures and methods of generating the same

In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

Dividing lithography exposure fields to improve semiconductor fabrication

A test layout structure including a first series of parallel metal lines in a first level, and a first series of contact structures in a second level, the second level being positioned above the first level, the first series of contact structures being positioned at known increments, where the increments are in a direction perpendicular to a length of the first series of parallel metal lines, and where one or more of the first series of contact structures is in electrical contact with one or more of the first series of parallel metal lines.

Measuring metal line spacing in semiconductor devices

A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

System and method of predicting problematic areas for lithography in a circuit design

A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Reticle data decomposition for focal plane determination in lithographic processes

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Stephen Edward Greco