Silicon Aquarius, Inc.

Silicon Sa

Stephen Earl Seitsinger

Wayland Bart Holland

Walland Bart Holland

A memory architecture includes an array of memory cells partitioned into a plurality of subarrays Each subarray includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline and each column associated with a pair of conductive half-bitlines The first sense amplifier is selectively coupled to selected pair of half-bitlines A second sense amplifier is selectively coupled to the selected pair of half-bitlines A first local I/O line is coupled to first sense amplifier and a second local I/O line is coupled to the second sense amplifier First and second sets of global I/O lines are selectively coupled to the first and second I/O lines

Memory architecture and systems and methods using the same

A memory,having an array,of rows and columns of dynamic memory cells,cells,of each row coupled to a refresh wordline,and an access wordline,and cells,of each column coupled to a refresh bitline,and an access bitline,Refresh circuitry,refreshes selected rows of cells corresponding to a refresh wordline,and a corresponding one refresh bitline,Access circuitry accesses selected cells of a selected row using corresponding access wordline,and corresponding one of the access bitlines,The access circuitry includes a new address detector of,for detecting receipt of a new address of said memory, a row decoder,for selecting access wordline in response to receipt of the new address and access sense amplifiers,and an access column decoder,accesses at least one cell along the selected wordline,using the corresponding access bitline

Dynamic random access memory system with a static random access memory interface and methods for using the same

A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.

Growing community of inventors

Plano, TX, United States of America

Stephen Earl Seitsinger