Cray Research, Inc.

Stephen E Nelson

Melvin C August

Eugene F Neumann

Richard R Steitz

James N Kruchowski

Diane M Christie

Galen C Flunker

David L Duxstad

Eugene N Reshanov

Stephen A Bowen

Stephen Cermak, Iii

Eric J Mueller

Mary A Nebel

Paul E Schroeder

Deanna M Dowdle

Danny J Cunagin

Dean B Dudley

Danny J Cunnigan

A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Method for adjusting clock skew

An apparatus for adjusting signal delay includes an input for receiving a signal to be delay adjusted. A delay circuit is connected to the input means for providing a plurality of selectable signal paths for various delay amounts for producing a delay adjusted signal therefrom. A delay selection circuit is connected to the delay circuit for selecting the signal path so as to select a delay amount and an output provides the delay adjusted signal to a load. Skew compensation is employed on the input and individually on each output to compensate for clock distribution network skew and intracircuit skews, respectively.

Method of adjusting for clock skew

A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Method of fabricating metallized chip carries from wafer-shaped

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'opening' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Integrated circuit chip carrier lid

An apparatus precisely adjusts the delay of a clock signal so as to reduce clock skew. The electronically programmable skew adjustment can be self-contained within a single IC package. The apparatus has an input for receiving a signal to be delay adjusted, delay elements including capacitive delay elements for providing multiple signal paths of various delays, delay selection circuitry for selecting the signal paths so as to select a delay amount, and an output to provide the delay adjusted signal to a load.

Skew-compensated clock distribution system

Computer cabinet

Method of fabricating metallized chip carriers from wafer-shaped

A flexible automated bonding apparatus electrically interconnects integrated circuit carriers, printed circuit boards, and other devices. A metallized interconnect pattern is deposited on the surface of the substrate. The metallized interconnects in the pattern span apertures created in the substrate using an excimer laser. Thus, the metallized interconnects can be electrically bonded through the apertures to elements lying underneath the substrate.

Flexible automated bonding method and apparatus

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'operating' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Chip carrier with terminating resistive elements

Method of making a chip carrier with terminating resistive elements

Growing community of inventors

Chippewa Falls, WI, United States of America

Stephen E Nelson