International Business Machines Corporation

Stephen E Bello

Kien Anh Hua

Jerome M Kurtzberg

Kevin Patrick McAuliffe

Richard Frank Rizzolo

David U Shorter

Edward B Eichelberger

Wilm Ernst Donath

Ting D Cheng

William M Chu

Robert Frederick Stucke

Emily Plachy

Ronald G Coleman

John O F Long

David R Pruett

John R Hattersley

Owen K Monroe

Gerald F Rollo

Tze-Rong Fu

Jih-Kwon Peir

John A Ludwig

Cyril A Price

Kathryn Priest Reece

Elizabeth A Vanderbeck

Paul Asobayire

John J Coleman

Rolf O Bergenn

Dilip K Barman

Anne E Bomford

Roger I McMillan

Thomas E Donegan

Joseph Hutt, Jr

San Y Han

R Bruce Shearer

Bhuwan Agrawal

Reini J Norman

John F Palmer

Ralph W Wilk

A method and system for forming and procuring an integrated solution to meet a set of requirements. The invention includes an electronic exchange for providing an information technology (IT) solution, comprising: a matching system for matching IT requirements with a set of candidate IT components that provide the IT solution; a supplier exchange system for interfacing with suppliers of the set of candidate IT components; and an exchange catalog for storing information relating to available IT components, including supplier information.

Method and system for matching complex customer requirements with provider solutions

A method for data processing can include associating at least one descriptor dimension with a data item. The descriptor dimension can represent a scale between a first subject and at least a second subject. A dimension value can be associated with the descriptor dimension to quantify a relationship between the data item and the first and second subjects.

Method of describing business and technology information for utilization

A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.

Fault-tolerant multiple processor system with signature voting

A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processors is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviors in the protocol when message packets depart or when they arrive.

Multiprocessor system with distributed memory

The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Timing driven placement

A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.

Two-level differential cascode current switch masterslice

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Kingston, NY, United States of America

Stephen E Bello