Agilent Technologies, Inc.

Hewlett-packard Company

Verigy (singapore) Pte. Ltd.

Verigy Pte. Ltd.

Stephen Dennis Jordan

Alan S Krech, Jr

John M Freeseman

John Howard Cook, Iii

Hsiu-Huan Shen

Edmundo De La Puente

Joel D Buck-Gengler

Preet P Singh

Catherine J Pfister

Hsui-Huan Shen

John M Freesman

Samuel U Wong

Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.

Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer

A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure counts are preloaded with the respective values of redundant rows and columns available for repairing the device. When failures in memory cells of the device are encountered, either during test, or during scan of an earlier generated error image, the row and column failure counts associated with the rows and columns containing the memory cell failures are decremented. At the end of a test, the value of the failure counts indicates whether the corresponding row or column contain any failures at all, whether the corresponding row or column is designated as a 'must-repair' row or column, and otherwise how many errors the corresponding row or column contain.

Memory device fail summary data reduction for improved redundancy analysis

Input to a device under test (DUT) is reconstructed. For each trigger cycle of a tester in which data is to be input to the DUT stimulus, data is prepared to be placed as stimulus on pins of the DUT. Response information obtained from the DUT during a previous trigger cycle is used to construct formatting information used to adjust a value of the stimulus data. Reconstruction information sufficient to reconstruct the stimulus data is stored. The reconstruction information includes the formatting information. The reconstruction information is used to reconstruct the stimulus data placed on the pins of the device under test.

Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test

The problem of sequentially 'squeezing' small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT. The arbitrary dynamic mapping is implemented by a collection of MUX's configured by data stored ahead of time in an SRAM, in accordance with what defining program constructs are encountered by the compiler as it processes the test program. A dynamic reverse mapper, also a collection of MUX's similarly controlled by an SRAM, serves as a de-serializer that assembles a sequence of received sub-vectors into a final received full-sized vector.

Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors

An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction is a binary word specifying a branch condition address and a conditional instruction. The branch unit has a programmable flag selection memory and a plurality of first flag selectors and determines in hardware whether to branch according to the conditional instruction. Each first flag selector accepts a plurality of available flags and selects a flag based upon contents in the flag selection memory. A second flag selector accepts the flags from the first flag selectors and selects one of the flags to present as a branch flag based upon the branch condition address. The branch flag indicates whether to branch to the destination address.

Method and apparatus for no-latency conditional branching

The various functions that are desirable for interior test memory within a memory tester are implemented in Memory Sets each serving as the host for one or sometimes more of such functions. For certain classes of testing a portion of interior test memory can be used as a Stimulus Log RAM that operates as an ideal DUT to create the correct conditions that are to exist in an actual DUT after testing. The actual part can then be tested, while the expected receive vectors are taken from the Stimulus Log RAM, and the comparison results sent to an ECR, Tag RAM's, etc., as usual. In this way the test program does not have to create or contain within itself the particular receive vectors that are the expected response from the applied stimulus.

Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM

Waveforms of input/output signals for a device under test (DUT) are simultaneously displayed. A user is presented with an interface that allows the user to specify different modes for capturing data for different input/output signals for the DUT. Data for the different input/output signals are captured in accordance with different data capture mechanisms dependent upon the different modes specified by the user. Based on the data, waveforms for each of the different input/output signals are simultaneously displayed.

Simultaneous display of data gathered using multiple data gathering mechanisms

A waveform for an input/output signal for a device under test (DUT) is displayed. Data for the input/output signal is captured in accordance with a first data capturing mechanism. The waveform for the input/output signal is displayed using the captured data. A user is provided with an interface that allows the user to select a portion of the waveform for recapture using a second data capturing mechanism. Data for a portion of the input/output signal, corresponding to the portion of the waveform selected for recapture, is recaptured. The recapturing of data is performed using the second data capturing mechanism. The waveform for the input/output signal is redisplayed. The data recaptured using the second data capturing mechanism is used for displaying the portion of the waveform selected for recapture. The data captured in accordance with the first data capturing mechanism is used for displaying remaining portions of the waveform not selected for recapture.

Recapture of a portion of a displayed waveform without loss of existing data in the waveform display

The data path into a post decode mechanism is altered to allow post decode to process data before or as that data is placed into a destination memory structure in interior test memory. Other data will continue to be first placed into a memory structure in interior test memory before being applied to the post decode mechanism. Extensive masking capability coupled with copies of error tables allow incremental post decode analysis for a new test, and avoids counting of errors in locations that are already known to have failed during previous tests. Both errors within words and bit errors can be accumulated. The post decode mechanism is often capable of producing multiple type of results from a single pass through the data, whether applied on the fly or from a structure in interior test memory. The post decode mechanism has counters that count down from pre-loaded values representing thresholds for deciding something about error activity. A counts of zero produces a terminal count flag. The values of the various terminal count flags are available at any time as data to be logged in interior test memory. Counters are often reloaded with an initial count at the conclusion of one test phase and in preparation for a subsequent phase. Some overhead may be saved and utility added by arranging for the counters to have respective initial value registers from which they may be reloaded upon receipt of a single command. The presence of the terminal count flag for a counter can inhibit the reload of the counter from its initial value register.

Memory tester with enhanced post decode

A method and apparatus for executing an integrated circuit (IC) test program including at least one calling instruction partitions at least one called subroutine into first and second subroutine portions, loads IC test program instructions into a primary memory, loads the first subroutine portion into the primary memory contiguous with the calling instruction, inserts a memory transfer access instruction after the first portion, and loads a remainder of the IC test program instructions into primary memory. The method then executes instructions from primary memory. Execution of the calling instruction in the primary memory causes the second subroutine portion to be loaded into a FIFO element from a secondary memory. The first subroutine portion executes from the primary memory. Execution of the memory transfer access instruction initiates fetching and executing the second portion of the called subroutine from a first-in-first-out (FIFO) element.

Method and apparatus for executing a program using primary, secondary and tertiary memories

The problem is to branch back to an appropriate location within a memory tester test program, and also restore its state of algorithmic control, when an error associated therewith occurs later in time at the DUT. Owing to delays in pipelines connecting the program execution environment to the DUT and back again. These delays allow the program to arbitrarily advance beyond where the stimulus was given. The arbitrary advance makes it difficult to determine the exact circumstances that were associated with the error. A branch based on the error signal can restart a section of the test program, but it is likely only a template needing further test algorithm control information that varies dynamically as the test program executes. The solution is to equip the memory tester with History FIFO's whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO. When the error flag is generated the desired program location and state information is present at the bottom of an appropriate History FIFO.

Algorithmically programmable memory tester with history FIFO's that aid in error analysis and recovery

A convolver includes a plurality of multipliers for multiplying pixel values of a convolution window by corresponding coefficients of a convolution mask to provide products, a summer for summing the products to provide a result and a memory for storing intermediate results. The convolver may be used to perform an N.times.N convolution in two or more passes. A first subset of pixel values of an N.times.N convolution window and a first subset of corresponding coefficients of an N.times.N convolution mask are supplied to the multipliers during a first pass of the N.times.N convolution. The summer provides an intermediate result for the first pass and stores the intermediate result in the memory. A second subset of pixel values of the N.times.N convolution window and a second subset of corresponding coefficients of the N.times.N convolution mask are supplied to the multipliers during a second pass of the N.times.N convolution. The summer combines the intermediate result and a result of the second pass to provide a final result or a second intermediate result for the N.times.N convolution.

Reconfigurable convolver circuit

A data processing system includes two or more parallel processors, a distributor and a combiner. The processors process input data items and generate corresponding output data items. The distributor includes an input counter for generating an ID corresponding to each of the input data items and a distributor for placing the input data items and the corresponding ID's in processor input words and distributing each of the processor input words to selected ones of the processors in accordance with a distribution algorithm. The combiner receives from the processors processor output words containing the output data items and the corresponding ID's. The combiner includes an output counter for generating an output count and comparators for comparing the output count with the ID's in the processor output words. The combiner further includes a combining circuit for transferring an output data item to an output data stream in response to detection by one of the comparators of a match condition between the output count and an ID corresponding to the output data item to be transferred. As a result, the data items in the output data stream have the same order as the data items in the input data stream.

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Stephen Dennis Jordan