Vlsi Technology, Inc.

Stephen David Nemetz

Mark Leonard Buer

John C Ciccone

An electronic device is delineated comprising, in combination, a Phased Lock Loop (PLL) having a charge pump, and a mixed signal circuit coupled in parallel to the charge pump. The mixed signal circuit includes analog circuitry for adding charge to and removing charge from capacitors in a Low Pass Filer (LPF) of the PLL. The mixed signal circuit also includes digital circuitry for controlling the initiation and termination of both the charging and discharging operations carried on by the analog portion of the mixed signal circuit. Upon a significant change in system frequency, the mixed signal circuit first fully discharges and then rapidly charges the capacitors in the LPF in a manner which results in a significant reduction in PLL locking time.

Phase-locked loop having improved locking times and a method of

A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

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Gilbert, AZ, United States of America

Stephen David Nemetz