Oki America, Inc.

Stephen David Gluyas

Alan P Dutcher

John L Scarrow

Joseph A Horanzy

A data transmission system transmits data from a first device to an interface device at a continuous rate and includes a first device for storing data and for transmitting data at a first data output rate. An interface device outputs data at a second data output rate different from the first data output rate. A preload buffer initially receives a predetermined amount of data from the first device and stores the initially received data. The preload buffer also transmits at least a portion of the initially received data at a third data output rate. The preload buffer receives additional data from the first device as the initially received data is transmitted from the preload buffer. A first buffer and a second buffer of generally equal size are sized to receive a single block of data from the preload buffer. The size of the single block of data is less than the predetermined amount of output data initially received and stored in the preload buffer. The first buffer first receives a block of data from the preload buffer and then transmits the block of data to the interface device. The second buffer first receives a block of data from the preload buffer and then transmits the block of data to the interface device. The first and second buffers are arranged so that when one of the buffers is receiving data from the preload buffer, the other buffer is transmitting data to the interface device. The interface device receives data from the first and second buffers at a rate sufficient for the interface device to continuously maintain the second data output rate.

Interface for transmitting graphics data to a printer from a host

An interface system for a printer and a print font chip includes an I/O port which is integral with the printer and receives from the printer address bits, data bits and control logic. A memory bus is electrically connected to the I/O port. The memory bus transmits and receives address bits, data bits and control logic from the I/O port. At least one print font chip is capable of generating address bits, data bits and control logic. Interfacing circuitry interfaces the memory bus and at least one font chip. The interfacing circuitry is bidirectional and capable of transmitting address bits, data bits and control logic between the bus and the font chip. Bus arbitration circuitry accesses the memory bus by at least one font chip. The arbitration circuitry is characterized in terms of priority. The font chips are assigned a predetermined priority by which access to the memory bus is determined.

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Berlin, NJ, United States of America

Stephen David Gluyas