Nvidia Corporation

Advanced Micro Devices Corporation

Emulex Design & Manufacturing Corporation

Stephen David Glaser

Marvin A Denman

Dennis K Ma

Eric Tyson

Mark Douglas Hummel

Christopher Joseph Pettey

Jonathan Owen

Michael Osborn

Denis J Foley

Benjamin Charles Serebrin

Asif Khan

Andrew Gregory Kegel

Robert Haskell Utley

Mike Osborn

Jon Nalley

Stephen Rousset

Tom Saeger

A method, computer program product, apparatus, and system are provided. Some embodiments may include transmitting a request to make one or more writes associated with an identification tag. The request may include the identification tag, the one or more writes, a first instruction to make the one or more writes to one of a plurality of persistence levels of a memory, and a second instruction to respond with at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory. Some embodiments may include receiving the at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory.

Systems, methods, and apparatuses for making writes to persistent memory

A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.

Safe communication mode for a high speed link

A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

System and method for early packet header verification

A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.

Lane-striped computation of packet CRC to maintain burst error properties

A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.

A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.

Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect

A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

System and method for enabling replay using a packetized link protocol

An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.

Tunnel suitable for multi-segment communication links and method therefor

An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

Atomic program verification

A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Programmable bridge header structures

A computer system includes a shared I/O device including functions providing access to device local memory space, and a plurality of roots coupled to the shared I/O device via a switch fabric. A first root assigns a first address in a first root memory space to a first function. A second root assigns a second address in a second root memory space to a second function. The switch fabric maps the first root memory space to a first portion of device local memory space and the second root memory space to a second portion of device local memory space. Subsequently, the switch receives a data transaction request from the first root targeted to the first address, translates the first address to a corresponding location in the first portion of the device local memory space based on the mapping, and routes the data transaction request to the I/O device.

Growing community of inventors

San Francisco, CA, United States of America

Stephen David Glaser