General Electric Company

Momentive Performance Materials Gmbh

Harris Corporation

Lockheed Martin Corporation

Diamond Innovations. Inc.

Gelcore, LLC

Stephen Daley Arthur

Peter Almern Losee

Kevin Sean Matocha

Alexander Viktorovich Bolotnikov

Peter Micah Sandvik

David Alan Lilienfeld

Zachary Matthew Stum

Reza Ghandi

Larry Burton Rowland

Steven Francis LeBoeuf

Mark Philip D'Evelyn

Victor A Temple

Ramakrishna Rao

Dong-Sil Park

Joseph Darryl Michael

Vinayak Tilak

Avinash Srikrishnan Kashyap

Kristi Jean Narang

Huicong Hong

Dale M Brown

Jody Alan Fronheiser

Ahmed Elasser

Eladio Clemente Delgado

James William Kretchmer

Victor Mario Torres

William Gregg Hawkins

Michael J Hartig

Tammy Lynn Johnson

Thomas R Anthony

Robert J Wojnarowski

Emad Andarawis Andarawis

Christopher James Kapusta

Stanton Earl Weaver, Jr

Richard J Saia

Kevin Matthew Durocher

Lionel M Levinson

Paul Alan McConnelee

Raymond Albert Fillion

Kanakasabapathi Subramanian

David Mulford Shaddock

Ernest Wayne Balch

David Richard Esler

Richard Alfred Beaupre

Suresh Shankarappa Vagarali

James Jay McMahon

John William Lucek

Nancy Cecelia Stoffel

Stanislav Ivanovich Soloviev

Abasifreke Udo Ebong

Gregory Keith Dudoff

Kevin Dean Matocha

Liangchun Yu

Jesse Berkley Tucker

William James Premerlani

Venkat Subramaniam Venkataramani

Thomas Frederick Soules

Thomas Bert Gorczyca

Michael Andrew De Rooij

Ljubisa Dragoljub Stevanovic

John M Neilson

Robert S Gilmore

Samhita Dasgupta

Homer H Glascock, Ii

Ivan Eliashevich

Donald L Watrous

Jeffrey Bernard Fortin

Hari S Venugopalan

Steven Alfred Tysoe

Charles Adrian Becker

Alexey V Vert

Kuna Venkat Satya Rama Kishore

Bryan S Shelton

Chen-Lun Hsing Chen

Peter V Gray

Somashekhar Basavaraj

Robert D Black

Sebastien Libon

Peter Almem Losee

Peter Michah Sandvik

Eric X Yang

Sabih Al-Marayati

Mark Philip D'evelyn

Roger Raymond Kovalec

Xian An (Andrew) Cao

Peter Sandvik

Peter Almren Losee

James Mcmahon

Richard Joseph Saia

Kuna Venkat Kishore

James Jay Mcmahon

Lionel Monty Levinson

Zachary Stum

Peter Losee

Kevin Matocha

Suresh Shankarappa Vagaralli

Thomas Richard Anthony

A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices

A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

Systems and methods for junction termination of wide band gap super-junction power devices

A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

High voltage semiconductor devices having improved electric field suppression

According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Semiconductor device and method for reduced bias threshold instability

The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.

Systems and methods for junction termination in semiconductor devices

A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

Systems and methods for unipolar charge balanced semiconductor power devices

Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

Techniques for fabricating planar charge balanced (CB) metal-oxide-semiconductor field-effect transistor (MOSFET) devices

A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC&#x2014;CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.

Systems and methods for termination in silicon carbide charge balance power devices

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Tapered gate electrode for semiconductor devices

Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.

Methods of fabricating high voltage semiconductor devices having improved electric field suppression

An insulated gate field-effect transistor (IGFET) device includes a semiconductor body () and a gate oxide (). The semiconductor body includes a first well region () doped with a first type of dopant and a second well region () that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section () and a relatively thicker interior section (). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region () of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact () disposed on the gate oxide.

Transistor and switching system comprising silicon carbide and oxides of varying thicknesses, and method for providing the same

A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.

Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices

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Stephen Daley Arthur