International Business Machines Corporation

Stephen Dale Wyatt

Ram Kelkar

Anthony Richard Bonaccio

Ilya I Novof

Hayden C Cranford, Jr

Joseph Andrew Iadanza

Sebastian Theodore Ventrone

Steven R Carlough

Gary A Van Huben

Susan M Eickhoff

Michael B Spear

Brandon R Kam

Terence B Hook

John Atkinson Fifield

Ivan L Wemple

Shiu Chung Ho

Faraydon Pakbaz

Tian Xia

Allen Prescott Haar

Christopher Ro

Donald E Strayer

Ping-Chuan Wang

Kerry Bernstein

Wagdi William Abadeer

Michael Anthony Sorna

Anjali R Malladi

John S Austin

Raminderpal Singh

Jeffery Howard Oppold

Giuseppe La Rosa

Kevin W Kolvenbach

Jonathan Henry Raymond

Richard F Keil

Michael A Soma

Kenneth Dean Short

Randall S Smith

Iiya I Novof

Michael P Corriveau

Jerry P Knickerbocker, Jr

Vishwanath A Patil

A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.

A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.

Double data rate (DDR) memory read latency reduction

Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Circuit and method for on-chip jitter measurement

A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.

Structure for transforming an input voltage to obtain linearity between input and output functions and system and method thereof

A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.

Structure for intrinsic RC power distribution for noise filtering of analog supplies

Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

Intrinsic RC power distribution for noise filtering of analog supplies

A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

Method and apparatus for dynamic characterization of reliability wearout mechanisms

Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

Structure for a high output resistance, wide swing charge pump

Designing integrated circuitry ('IC') includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry

Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

High output resistance, wide swing charge pump

A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to 'lock' the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.

Sub-picosecond multiphase clock generator

An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

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Jericho, VT, United States of America

Stephen Dale Wyatt