Intel Corporation

Stephen D Snyder

Leonard P Guler

Urusa Alaan

Michael Harper

Tahir Ghani

Biswajeet Guha

Richard E Schenker

William Hsu

Stephanie A Bojarski

Sam Sivakumar

Shu Zhou

Vivek Thirtha

Nitesh Kumar

Achala Bhuwalka

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

Gate-all-around integrated circuit structures having fin stack isolation

Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

Non-planar transistors with channel regions having varying widths

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Portland, OR, United States of America

Stephen D Snyder