The University of New Mexico

Other

Stephen D Hersee

Steven Roy Julien Brueck

Daniel F Feezell

Seung-Chang Lee

Xin Wang

Xinyu Sun

Gregory M Peake

David Zubia

Andrew M Sarangan

Gabriel P Lopez

Majeed M Hayat

Saleem H Zaidi

Linnea K Ista

Pradeep Sen

Michael J O'Brien

David Emin

Eric A Armour

Ronghua Wang

Terrance L Aselage

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

Semiconductor product comprising a heteroepitaxial layer grown on a seed area of a nanostructured pedestal

Method of making heteroepitaxial structures and device formed by the method

Device with heteroepitaxial structure made using a growth mask

Method of forming a seed area and growing a heteroepitaxial layer on the seed area

Exemplary embodiments provide solid-state microscope (SSM) devices and methods for processing and using the SSM devices. The solid-state microscope devices can include a light emitter array having a plurality of light emitters with each light emitter individually addressable. During operation, each light emitter can be biased in one of three operating states including an emit state, a detect state, and an off state. The light emitter can include an LED (light emitting diode) including, but not limited to, a nanowire based LED or a planar LED to provide various desired image resolutions for the SSM devices. In an exemplary embodiment, for near-field microscopy, the resolution of the SSM microscope can be essentially defined by the pitch p, i.e., center-to-center spacing between two adjacent light emitters, of the light emitter array.

Solid-state microscope for selectively imaging a sample

Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Nanowires, nanowire networks and methods for their formation and use

Method of making a heteroepitaxial layer on a seed area

According to various embodiments, the present teachings include an array of nanowire devices. The array of nanowire devices comprises a readout integrated circuit (ROIC). An LED array is disposed on the ROIC. The LED array comprises a plurality of LED core-shell structures, with each LED core-shell structure comprising a layered shell enveloping a nanowire core, wherein the layered shell comprises a multi-quantum-well (MQW) active region. The LED array further comprises a p-side electrode enveloping the layered core-shell structure and electrically connecting the ROIC, wherein each p-side electrode has an average thickness ranging from about 100 nm to about 500 nm. A dielectric layer is disposed on the plurality of LED core-shell structures, with each nanowire core disposed through the dielectric to connect with an n-side semiconductor that is situated on the dielectric.

Phase-coupled arrays of nanowire laser devices and method of controlling an array of such devices

Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Integration of LED driver circuit with LED

Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

Pulsed growth of catalyst-free growth of GaN nanowires and application in group III nitride semiconductor bulk material

Growing community of inventors

Albuquerque, NM, United States of America

Stephen D Hersee