Altera Corporation

Stephen D Brown

Deshanand Pratap Singh

Terry Borer

Valavan Manohararajah

Gabriel Quan

Gordon Raymond Chiu

Vaughn Betz

Ivan Blunno

Chris Sanford

David Karchmer

Andrew Leaver

Kevin Chan

Ian Chesal

Jordan Swartz

Caroline Pantofaru

David Wolk Mendel

Gregg William Baeckler

James G Schleicher

Babette Van Antwerpen

Richard Yuan

Mike Hutton

Ivan Hamer

Boris Ratchev

Karl Schabas

Yaska Sankar

Sergey Yuryevich Shumarayev

Bruce B Pedersen

Wei-Jen Huang

Tony K Ngai

Vinson Chan

Tim Michael Vanderhoek

James Park

Paul McHardy

Shawn Malhotra

Przemek Guzy

Steven Caranci

Jason Govig

Minh V Mac

Alexander Grbic

Subianto Windoro

Irene Sujanto

Sheac Yee Lim

Jimmy Kuo

Rebecca Katzin

Zvonko Vranesic

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Method and apparatus for performing multiple stage physical synthesis

A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Method and apparatus for performing compilation using multiple design flows

M/A for performing incremental compilation using top-down and bottom-up design approaches

A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.

Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

An instruction trace is segmented into a number of contiguous instruction segments, such that each boundary between adjacent instruction segments is defined by a branch instruction. A segment identifier is assigned to each instruction segment, such that each instruction segment having identical content is assigned a same segment identifier. Using the assigned segment identifiers, the instruction trace is translated into a sequence of segment identifiers. The sequence of segment identifiers is then iteratively consolidated into a prime form that does not include a repetition of a heterogeneous pair of consecutive segment identifiers. The prime form of the sequence of segment identifiers is then rendered in a graphical format.

Methods for instruction trace decomposition

Systems and methods are provided for mapping logic functions from logic elements ('LEs') into synchronous embedded memory blocks ('EMBs') of programmable logic devices (&#x201c;PLDs&#x201d;). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

Systems and methods for mapping arbitrary logic functions into synchronous embedded memories

A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.

Method and apparatus for performing post-placement routability optimization

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

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Toronto, Canada

Stephen D Brown