Cabletron Systems, Inc.

Stephen D Augusta

Mark J Donovan

Christopher J Oliver

Benjamin J Brown

James E Burgess

A data buffering storage circuit automatically allocates a portion of shared storage area to the direction in which data buffering is required. This scheme allows use of fewer parts on a piece of networking hardware, which in turn lowers the cost, simplifies the design, and uses existing on-board memory in a more efficient manner. In at least one embodiment, a first area is allocated to the buffering of a first port of a network switch, a second memory area is allocated to the buffering of a second port of the network switch, and a third area is shared among the buffering of the first port and the buffering of the second port.

Method and apparatus for adaptive port buffering

A packet of data is received from a LAN and transmitted over a WAN, by retaining the native LAN frame format of the packet during transmission across the WAN. Thus, LAN data may be transmitted over a SONET point-to-point link within a WAN network without the interim steps of creating ATM cells or other WAN transport packaging protocols. Instead, the LAN data may be transmitted directly over the SONET link as raw data, and reconstructed directly at the receiving end of the SONET link. A first buffer stores data from the LAN so that a corresponding packet size may be determined, and a second buffer stores data from the WAN to account for any speed difference between the LAN circuitry and WAN circuitry.

Growing community of inventors

Nashua, NH, United States of America

Stephen D Augusta