Xilinx, Inc.

Rosemount Inc.

Rosemont Inc.

Stephen D Anderson

David Erich Tetzlaff

Brian Lee Westfield

Brian Taylor Brunn

Bennett L Louwagie

Todd A Piechowski

Gregory C Brown

Michael A Nix

Jinghui Lu

Matthew L Bibee

Shahriar Rokhsaz

Roger L Frick

Michael J Gaboury

Moises Emanuel Robinson

Ahmed Younis

Theodore Henry Schnaare

Kevin B Moore

Firas Najeh Abughazaleh

Brian Scott Junk

Khaldoun Bataineh

Theodore L Johnson

Yvette P Lee

Gabriel A Maalouf

Michael Ren Kent

Paul D Kammann

Michael Maas

Glen E Monzo

Daniel V Hulse

Kazi S Hossain

Michael A Orman

Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edges of a data signal and drives the associated error term to zero. The new BE-ZFE is appropriately implemented within communication systems that are phase (or jitter) noise limited. Some examples of such communication systems include high-speed serial links one type of which serviced using a SERDES (Serializer/De-serializer) where data that is originally in a parallel format is serialized into a serial data stream and then subsequently de-serialized back into a parallel data stream.

Bit-edge zero forcing equalizer

A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

Combined decision feedback equalization and linear equalization

A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Receiver operable to receive data at a lower data rate

A method and apparatus for combining statistical eye channel compliance methods with linear continuous-time equalization. A set of equalizer parameters is processed with measured channel parameters to create a set of modified parameters that are then used with a statistical eye algorithm. This technique allows for the addition of linear continuous-time equalization with or without modification of the existing statistical eye algorithm.

Method and apparatus for combining statistical eye channel compliance methods with linear continuous-time equalization

Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.

Method of adaptive equalization for high-speed NRZ and multi-level signal data communications

A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Integrated high-speed serial-to-parallel and parallel-to-serial transceiver

Conversion circuitry for use in a process control system is adapted for coupling to a primary process control loop. Digital receiver circuitry in the conversion circuitry receives a digital signal transmitted over the primary process control loop from a field transmitter and responsively provides a digital output. A microprocessor receives the digital output and responsively provides a secondary loop control output. Secondary loop control circuitry for coupling to a secondary process control loop receives the secondary loop control output from the microprocessor and responsively controls current flowing through the secondary process control loop. The current flowing through the secondary process control loop is related to the digital signal transmitted by the field transmitter.

Conversion circuit for process control system

A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals. When the selector disconnects the filter from between the phase detector and the demodulator, the demodulator demodulates non-coherent modulated signals and the phase detector supplies a phase signal representing the slope of the phase of the demodulated signal.

Method and apparatus for demodulating coherent and non-coherent modulated signals

A field instrument includes an input circuit having a transistor bridge rectifier which is couplable to a power supply. The transistor bridge rectifier is configured to provide power from the power supply to a remainder of the field instrument.

Power supply input circuit for field instrument

A three wire transmitter bidirectionally communicates AC signals to and from a first external device and sends DC signals to a second external device. The transmitter includes a communication circuit which is energized from power and common terminals and includes memory storage for transmitter status and a process variable (PV). The communication circuit receives a sensor output indicative of the PV and provides the DC signal and the AC signal to a signal terminal which connects to both external devices, and also receives AC signals from the first external device. The communications circuit has a characteristic AC impedance between the signal and common terminals over an AC frequency range for receiving and transmitting AC signals to and from the first external device so that the receiving signals are not shorted out and so the transmitted signals can be received. The communications circuit has a characteristic DC impedance between the signal and common terminals over a range of frequencies which include DC and typically extend to approximately 20 Hz. The characteristic impedance is substantially lower than the impedance of the second external device which receives DC signals so that the accuracy of the DC signal is not compromised.

Three wire low power transmitter

Growing community of inventors

Minnetonka, MN, United States of America

Stephen D Anderson