Wave Computing, Inc.

Mips Holding, Inc.

Stephen Curtis Johnson

David John Simpson

Richard D Trauben

Keith Mark Evans

Richard Douglas Trauben

Benjamin Wiley Melton

Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A plurality of dimensions from a tensor is flattened into a single dimension. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. A direct memory access (DMA) engine coupled to the one or more processor clusters is configured. Addresses are generated based on the unique address space descriptors and the common address space descriptor. The plurality of dimensions can be summed to generate a single address. Memory is accessed using two or more of the addresses that were generated. The addresses are used to enable DMA access.

Processor cluster address generation

Techniques for data manipulation using processor cluster address generation are disclosed. One or more processor clusters capable of executing software-initiated work requests are accessed. A direct memory access (DMA) engine, coupled to the one or more processor clusters, is configured, wherein the DMA engine employs address generation across a plurality of tensor dimensions. A work request address field is parsed, where the address field contains unique address space descriptors for each of the plurality of dimensions, along with a common address space descriptor. DMA addresses are generated based on the unique address space descriptors and the common address space descriptor. Memory using two or more of the DMA addresses that were generated is accessed, where the two or more DMA addresses enable processing within the one or more processor clusters.

Multidimensional address generation for direct memory access

Techniques are disclosed for data manipulation within a reconfigurable computing environment for data flow graph computation using exceptions. Processing elements are configured within a reconfigurable fabric to implement a data flow graph. The processing elements are loaded with process agents. Valid data is executed by a first process agent on a first processing element, where the first process agent corresponds to a starting node of the data flow graph. A second processing element detects that an error exception has occurred, where a second process agent is running on the second processing element. A done signal to a third process agent is withheld by the second process agent, where the third process agent is running on a third processing element. The second process agent raises an interrupt request, where the interrupt request is based on the detecting that an error exception has occurred.

Data flow graph computation using exceptions

Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a '0' state when a '1' is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a &#x201c;0&#x201d; state when a &#x201c;1&#x201d; is applied to the NCL complement input.

Growing community of inventors

Morgan Hill, CA, United States of America

Stephen Curtis Johnson