Telefonaktiebolaget Lm Ericsson (publ)

Stephen Chow

Ranjit Joseph Rozario

Michael Feng

Edmund C Chen

Edward Ho

Thomas C Yip

Patrick Wang

Sun Den Chen

Ramanathan Lakshmikanthan

Brian Alleyne

Srivi Dhruvanarayan

Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

On-chip packet cut-through

A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Hierarchical pipelined distributed scheduling traffic manager

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Monte Sereno, CA, United States of America

Stephen Chow