Sony Corporation

Sony United Kingdom Limited

Sony Group Corporation

Stephen Charles Olday

James Hedley Wilkinson

Karl James Sharman

Nicholas Ian Saunders

Yoshihiro Okamoto

Jian-Rong Chen

David Berry

Rajan Bhandari

Matthew Compton

Manish Devshi Pindoria

Mitsuaki Sugimoto

A packet-based video network includes: plural packetized video data nodes; a packet switch configured to switch from one of video packet routes to another of video packet routes; and a video synchronizer configured to synchronize the video frame periods of at least nodes acting as packetized video data sources; wherein: each node acting as a packetized video data source is configured to launch onto the network packetized video data such that, for at least video frame periods adjacent to a switching operation: the node launches onto the network packetized video data required for decoding that frame during a predetermined active video data portion of the video frame period, and the node does not launch onto the network packetized video data required for decoding that frame during a predetermined remaining portion of the video frame period; and the switching operation is implemented during the predetermined remaining portion.

Video network

Image processing apparatus comprises a demosaic processor for receiving a video signal comprising pixel data from an array of photosensors each having a respective color filter so as to restrict the sensitivity of that photosensor to a primary color range selected from a set of three or more primary color ranges, the array being such that the photosensors in alternate rows are sensitive to a first primary color range, and photosensors in intervening rows are sensitive to the other primary color ranges. The pixel data including pixel data from a first subset of the rows sensitive to the first primary color range, the first subset being the same from image to image of the video signal; and pixel data from a second subset of the rows of photosensors sensitive to the other primary color ranges, the second subset changing from image to image of the video signal.

Image processing

The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Frequency synchronisation of clocks

A digital signal comprises data blocks. Each data block includes a header containing data relating to the block and a plurality of slots. Each slot has a slot header relating to the slot and a data packet. A plurality of data packets contains at least a first part and subsequent parts of the digital signal. A first slot includes the first part of the digital signal and a reference time defining a time of production of the first part. Each subsequent slot contains a subsequent part of the digital signal and timing information defining a time of production of the subsequent part relative to the reference time.

Digital signal processing and signal format

A buffer (4) has a read and write control (8, 7), an input (6), an output (5), and a transfer port (9). An SCSI interface (20) is coupled to port (9) and the read/write control (8, 7). The SCSI interface (20) implements transfer commands for transfers via the port 9 with an undefined delay. An RS 422 interface is coupled to the read/write control (8) and implements transfer commands for transfers via the input 6 and output 5, the commands being implemented with a small, defined delay synchronously with a video sync signal (SYNC).

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Basingstoke, United Kingdom

Stephen Charles Olday