Advanced Micro Devices Corporation

Stephen Charles Kromer

Richard T Witek

Kathryn Jean Hoover

James Joseph Montanaro

Thang M Tran

William M Johnson

Teik-Chung Tan

Gopi Ganapathy

Suzanne Plummer

Joe Peters

An integrated circuit () includes a firewall input terminal, a first circuit (), and a second circuit (). The firewall input terminal is for receiving a firewall input signal. The first circuit () is coupled to a first power supply voltage terminal () and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (), to the firewall input terminal (), and to the first circuit (). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Integrated circuit with a hibernate mode and method therefor

A data processor () has a pipelined execution unit (). Whether a first instruction is one of a class of instructions wherein as a result of execution of the first instruction the contents of an operand register will be stored in a destination register is determined. A second instruction that references the destination register is received before a completion of execution of the first instruction. The second instruction is executed using the contents of the operand register without stalling the second instruction in the pipelined execution unit ().

Method and data processor with reduced stalling due to operand dependencies

A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Method and apparatus for lowering bus clock frequency in a complex integrated data processing system

An improved signal line routing scheme includes a plurality of dynamic signal lines disposed in parallel to each other, and a plurality of static signal lines disposed in parallel to each other and also disposed in parallel with the plurality of dynamic signal lines, wherein at least one of the plurality of static signal lines is disposed immediately adjacent to each one of the plurality of dynamic signal lines.

High density dynamic bus routing scheme

A data latching mechanism uses Column Address Strobe (CAS) signals to effect one-cycle DRAM page-mode access at high operation frequency.

DRAM access system and method

A microprocessor having an option to select one of multiple clock frequencies as an internal clock frequency. The microprocessor reconfigures the speed paths of internal function circuit on the basis of a clock selection signal used to select the internal clock frequency. In this manner the minimum number of internal clock cycles are used to carry out the function of the function circuit despite the particular internal frequency selected.

Self configuring speed path in a microprocessor with multiple clock

The invention facilitates testing of electrical circuitry which includes a circuit receiving a signal asynchronous with respect to the circuit clock. The exact clock pulse on which the asynchronous signal is asserted may be difficult or impossible to predict even when the circuitry inputs are known. However, a range of pulses can be determined during which the asynchronous signal is asserted. The sampling of the asynchronous signal is blocked until the end of the range of pulses. If it is known that at the end of the range of pulses the asynchronous signal should still be asserted provided that the circuitry functions properly, the asynchronous signal is sampled at the end of the range of pulses. Alternatively, if the asynchronous signal can be deasserted by the end of the range of pulses, the assertion of the asynchronous signal is detected and latched by the asynchronous signal pulse detector, and at the end of the range of pulses the circuit samples the value latched by the pulse detector. In both alternatives, the end of the range of pulses facilitates an unabiguous clock pulse at which the asynchronous signal should be sampled.

Testing of electrical circuits

An apparatus for synchronizing a plurality of asynchronous circuits during testing operations is provided. The apparatus includes first and second clock inputs, a test mode input, and an output. The apparatus receives a first clock signal from a first clock at the first clock input, and a second clock signal from a second clock at the second clock input. Responsive to the state of a test mode signal at the test mode input, the apparatus generates either the first clock signal or the second clock signal at the output. A first circuit is arranged to be driven by the output of the apparatus, while a second circuit is driven by one of the first or second clocks. Consequently, the first and second circuits are driven by different clocks when the test mode signal is in one state, and driven by the same clock when the test mode signal is in another state. Because the first and second circuits are driven by the same clock during testing operations, the timing of the communications between the circuits is predictable, making it possible to perform certain testing techniques that are not possible when the timing of inter-circuit communication is not predictable.

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Austin, TX, United States of America

Stephen Charles Kromer