Cisco Technology, Inc.

Stephen Charles Hilla

Kenneth H Potter

Jonathan Rosen

Timothy F Masterson

John William Marshall

William E Jennings

Barry Scott Burns

Nathan Allen Mitchell

Rafael Mantilla Montalvo

Karen A Szypulski

Timothy Marsteiner

Jorge Manuel Gonzalez

James M Edwards

Controlling a transmission rate of packet traffic includes receiving packets from a network processor. The packets are stored in a buffer associated with a processor. If an occupancy level of the buffer is greater than a predetermined threshold, it is determined that the processor is congested. A message is transmitted to the network processor indicating the processor is congested.

Controlling a transmission rate of packet traffic

The invention comprises system and method for offloading a processor tasked with calendar processing of channel status information. The method comprises multiplexing channel status information received from a plurality of physical interfaces; grouping the channels based on bandwidth; comparing current and previous status information of a group of channels in a first memory; sending current channel status to the processor only if the status of any of the channels in the group has changed; and periodically synchronizing channel status information in the first memory to status information in the processor's memory. The system comprises: multiplexer to combine channel status information received from the interfaces and means for grouping, based on bandwidth, the channels; hardware assist engine to send current channel status to the processor only if channel status has changed; and device to synchronize channel status information in the hardware assist engine to status information in the processor's memory.

System and method for offloading a processor tasked with calendar processing

Techniques for distributing data packets over a network link bundle include storing an output data packet in a data flow queue based on a flow identification associated with the output data packet. The flow identification indicates a set of one or more data packets, including the output data packet, which are to be sent in the same sequence as received. State data is also received. The state data indicates a physical status of a first port of multiple active egress ports that are connected to a corresponding bundle of communication links with one particular network device. A particular data flow queue is determined based at least in part on the state data. A next data packet is directed from the particular data flow queue to a second port of the active egress ports. These techniques allow a more efficient use of a network link bundle.

Method and apparatus for dynamic load balancing over a network link bundle

A load balancing mechanism and technique that monitors a memory interface associated with a processor resource in a processor pool associated with at least one node of a computer network. The monitoring determines the actual load activity executed by the processor during a specified period of time. The mechanism comprises a hardware access monitor configured to determine the true activity of each processor resource. The access monitor tracks certain memory requests over the memory interface and stores the requests in a counter assigned to each processor. The access monitor then collects statistics from each processor resource of the pool and provides those statistics to a central load balancing resource for use when determining assignment of loads (tasks) to the various processor resources.

System and method for process load balancing in a multi-processor environment

A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the set of buffers; in the illustrative embodiment, only transient data may be stored in these buffers. The mechanism further blocks write requests directed to these predetermined memory buffers from propagating to the secondary cache, thereby precluding storage of transient data in the cache.

Cache blocking of specific data to secondary cache with a first and a second OR circuit

An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.

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Raleigh, NC, United States of America

Stephen Charles Hilla