Lucent Technologies Inc.

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Agere Systems Guardian Corp.

Stephen Carl Kuehne

Alvaro Maury

Yi Ma

David W Kelly

Scott Francis Shive

Daniel Charles Kerr

Ross Wilson

Isik C Kizilyalli

Jason P Brenden

Brittin C Kane

Alan Sangone Chen

Hao Fang

David Fitzgerald

Minseok Oh

Daniel James Dolan, Jr

Daniel J Dolan, Jr

Harley Burger

Michael A Laughery

Mahjoub Ali Abdelgadir

Jean Ling Lee

Robert Ys Huang

Jane Qian Liu

Nathan M Rudd

Stefanie Chaplin

David Kou-Fong Hwang

Xiaojun Deng

Various embodiments of the present invention provide systems and methods for determining contact with a storage medium. As an example, a data storage system is disclosed that includes: a head assembly and a data processing circuit. The head includes a head disk interface sensor operable to provide a contact signal indicating contact between the head and a storage medium disposed in relation to the head. The data processing circuit is operable to process the contact signal to yield an indication of a contact between the storage medium and the head.

Systems and methods for detecting head contact

An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

Integrated circuit with depletion mode JFET

A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

Head-specific standby modes for disk drive preamplifiers and the like

A demagnetizer for an inductive load having a driver circuit including at least one transistor and a ramp-down voltage source switchably connected to the driver circuit, so that when the ramp-down voltage source is connected to the transistor, it drives the voltage of the transistor below its threshold voltage.

Write head demagnetizer

The present invention provides a semiconductor device including large topography alignment marks, and a method of manufacture therefor. The method of manufacturing the semiconductor device includes forming an isolation trench and an alignment mark in a substrate to a substantially common depth, and forming an etch stop layer in the alignment mark.

Alignment mark having a protective oxide layer for use with shallow trench isolation

The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region. As a result, the channel region becomes non-conductive, and the first conductive connection is, therefore, insulated from the second conductive connection.

Stable memory device that utilizes ion positioning to control state of the memory device

During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art. As such, the duration of CMP processing can be correspondingly shorter, resulting in polished semiconductor wafer surfaces with greater uniformity than that provided by the prior art.

Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing

A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an originally undoped film, resulting in a uniform boron distribution within the structure, thereby rendering the structure resistant to vertical and lateral diffusion of the boron during subsequent processing at elevated temperatures.

In-situ boron doped polysilicon with dual layer and dual grain structure

The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.

Shallow trench isolation

In the fabrication of an integrated circuit, undesirable bird's beak pull back due to damage caused during ion implantation is alleviated by means of rapid thermal annealing step prior to chemical etching.

Process for improving device yield in integrated circuit fabrication

Growing community of inventors

Orlando, FL, United States of America

Stephen Carl Kuehne