Hughes Aircraft Company

Other

Stephen C Su

Ronald M Finnila

Warren Schultz

A low impedance load is switched between a power supply source and ground through a series connected power MOSFET the conduction of which is controlled by a switching circuit. The switching circuit includes a linear loop that regulates the switch voltage to a minimum value to produce current flow through the load and the MOSFET. In addition, the switching circuit includes a current supply placed in parallel to the MOSFET which is set to supply a minimum predetermined current that is representative of the value of current flow through the load under an open load condition. If the load current falls below this set current value an open load status flag is provided by the switching circuit as the loop is no longer in regulation.

Switching circuit

A method and apparatus for improving the operation of infrared detectors of a type generally characterized by a semiconductive substrate of a first conductivity type which includes a detection region defined or bounded by a heavily doped backside electrode and buried layer of the first conductivity type. A charge coupled device (CCD) readout structure for transfers charge in an epitaxial layer of second conductivity type which overlies the substrate, and the detector further includes a heavily doped layer of the second conductivity type positioned between the epitaxial layer and the substrate to shield the charge carriers of the substrate from the CCD voltages. Means are provided by the present invention for the injection of minority charge carriers into the epitaxial region which are subsequently transferred to output means by the CCD. The substrate is biased so that a portion of the flow of minority carriers in the epitaxial layer will be diverted toward the backside electrode when the detection region is raised to conduction by the incidence of photon energy so that a subtractive indication of the radiation is obtained while harmful double injection and attendant substrate breakdown are avoided.

Signal detection method for IR detector having charge readout structure

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises two epitaxial layers grown on an extrinsically doped silicon substrate. The detectors are formed in and extend through the substrate, the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The collection of charges takes place on a first buried layer formed around a portion of the first epitaxial layer-substrate interface, and the charges are then transferred through a second buried layer of the same conductivity type to a conducting surface layer on the upper portion of the second epitaxial layer. The signal readout function is performed by a charge coupled device shift register constructed in the second epitaxial layer by providing selectively spaced electrodes in an insulating layer. Carriers generated in the detector by incident infrared radiation are collected into the first buried layer and then pass through the second buried layer to the surface layer and they are injected therefrom into the CCD shift register and are detected at the output. The monolithic construction and the use of an epitaxial layer to form the CCD shift register result in high yield and high efficiency devices. The use of two epitaxial layers in the device improves its responsivity, its fill factor and better isolates the operation of its CCD circuits from its detector elements.

Monolithic extrinsic silicon infrared detector structure employing

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises an epitaxial layer grown from an extrinsicly doped silicon substrate. The detectors are formed in and extend through the substrate the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The signal readout function is performed by a charge coupled device shift register constructed in the epitaxial layer by separating electrodes from it in an insulating layer formed on it. Carriers generated in the detecor by incident infrared radiation are directly injected into the CCD shift register and detected at the output end. The monolithic construction and the use of an epitaxial layer to form the CCD shift register results in low cost, high yield and high efficiency devices.

Monolithic extrinsic silicon infrared detectors with charge coupled

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises an epitaxial layer grown on an extrinsically doped silicon substrate. The detectors are formed in and extend through the substrate, the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The collection of charges takes place on a buried layer formed around a portion of the epitaxial layer-substrate interface, and the charges are then transferred through a surface layer of the same conductivity type to the surface of the epitaxial layer. The signal readout function is performed by a charge coupled device shift register constructed in the epitaxial layer by providing selectively spaced electrodes in an insulating layer. Carriers generated in the detector by incident infrared radiation are collected into the buried layer and then pass through the surface layer, are injected therefrom into the CCD shift register and are detected at the output. The monolithic construction and the use of an epitaxial layer to form the CCD shift register result in high yield and high efficiency devices. The planar surface of the device improves the aluminum step coverage for a more reliable device, and the use of the buried layer improves the fill factor of the detector.

Monolithic extrinsic silicon infrared detectors with an improved charge

The specification describes a self-aligning masking technique for the fabrication of charge coupled device-metal oxide semiconductor (CCD/MOS) transistor combinations. Both the CCD devices and the output MOS transistors are formed on the same semiconductor substrate during the same processing steps. Two layers of polycrystalline silicon, isolated from each other by a layer of dielectric material and isolated from the semiconductor substrate by another dielectric layer are used to form two sets of partially overlapping semiconductor strips. These strips and predetermined portions of the substrate are then doped, with a conductivity determining impurity opposite the conductivity type of the substrate. This process produces two self-aligned sets of gate electrodes for a two-phase or a four-phase CCD device and also produces two output self-aligned gate field effect transistors at the end of the CCD array.

Method for fabricating self-aligned CCD devices and their output

There is disclosed a circuit for removing the DC or background representing charge component of a signal to be passed through a charge coupled device shift register without degrading the information carried by the AC component of the signal. Such a circuit may, for example, be used to remove the constant background illumination component of the input from a semiconductor imaging device to increase the contrast ratio of the image signal. The circuit comprises two electrode defined potential wells or buckets formed in a semiconductor substrate with a control gate between them and a transfer gate which controls the flow of the charges in the first bucket to a P-N junction. Like the well defining electrodes, the control gate and transfer gate are electrodes separated from the semiconductor substrate by an insulation layer. The transfer gate functions as a channel switch to control the flow of the background charges from the first bucket through the P-N junction to an external drain in discrete quantized increments under the control of an appropriate clock voltage on the transfer electrode. This subtraction of the DC component from the signal passing through the shift register results in a reduction in the size of the storage electrodes required to transmit a given quantity of signal charge through the shift register for fixed clock voltages and thereby makes more economical use of the chip area.

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Huntington Beach, CA, United States of America

Stephen C Su