Ati International Srl

C-cube Microsystems, Inc.

Other

Pasternak Solutions, LLC

Chromatic Research, Inc.

Imagination Technologies Limited

Caustic Graphics, Inc.

Ati Technologies Ulc

Advanced Micro Devices Corporation

Nvidia Corporation

Broadband Royalty Corporation

Pastemak Solutions LLC

Ati International Srl, Beaumont House

Advanced Silicon Technologies LLC

Stephen C Purcell

Scott A Kimura

Korbin S Van Dyke

Nital P Patwa

Ryan R Salsbury

Luke Tilman Peterson

James Alexander McCombe

David E Galbi

Parin Bhadrik Dalal

Don A Van Dyke

Chad Edward Fogg

Niteen Aravind Patkar

Frank H Liao

Didier J Le Gall

Yvonne C Tse

John S Yates, Jr

Paul Henry Hohensee

David Reese

Paul W Campbell

Shalesh Thusoo

Christopher Thomas Cheng

Ali Alasti

Steve C Hale

Rajeshwaran Selvanesan

Subroto Bose

John S Thomson

Sanjay Mansingh

Stephen C Hale

Jason Rupert Redgrave

Sean Matthew Gies

Govind V Malalur

Michael C Adler

P Michael Farmwald

T R Ramesh

James A Mccombe

Mauro Bonomi

Sandeep Nijhawan

Christopher Philip Alan Tann

Matthew F Storch

Alexandre Balkanski

DeForest Tovey

Gurjeet Singh Saund

Dale R Jurich

David L Reese

Dee Tovey

Cüneyt Özdaş

James W Kirkpatrick, Jr

Wen-Chang Hsu

Mark Wood-Patrick

Andrew C Hung

Eric Chi-Wang Chai

James Thomas Battle

Mark L Wood Patrick

Andy C Hung

Daniel A Kartch

Korbin Van Dyke

Paul H Hohensee

Paul Campbell

Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set of input data elements and produce results. These results can be that the data elements can be categorized into different subsets, where each subset requires different processing as a next step. The data elements of these different subsets can be coalesced so that they are contiguous in a results set. The results set can be used to schedule additional computation, and if there are empty locations of a scheduling vector (after accounting for the members of a given subset), then those empty locations can be filled with other data elements that require the same further processing as that subset.

Ray tracing in computer graphics using intersection testing at selective resolution

Compacting results vectors between stages of graphics processing

Aspects include systems, methods, and media for implementing methods relating to increasing consistency of results during intersection testing. In an example, vertexes define edges of primitives composing a scene (e.g., triangles defining a mesh for a surface of an object in a 3-D scene). An edge can be shared between two primitives. Intersection testing algorithms can use tests involving edges to determine whether or not the ray intersects a primitive defined by those edges. In one approach, a precedence among the vertexes defining a particular edge is enforced for such intersection testing. The precedence causes an intersection tester to always test a given edge in the same orientation, regardless of which primitive defined (at least in part) by that edge is being intersection tested.

Systems and methods for primitive intersection in ray tracing

An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Variable-length code decoder

Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Scheduling of graphics operations for concurrent execution on a computer may increase throughput. In aspects herein, constituent graphics operations are scheduled in groups, having members selected according to disclosed aspects. Processing for specific graphics operations in a group can be deferred if all the operations in the group cannot be further tested concurrently. Graphics operations that have been deferred are recombined into two or more different groups and ultimately complete processing, through a required number of iterations of such process. In one application, the performance of the graphics operations perform a search in which respective 1:1 matches between different types of geometric shapes involved in the 3-D scene are identified. For example, closest intersections between rays and scene geometry can be identified by processing scheduled according to disclosed aspects.

Architectures for concurrent graphics processing operations

Systems, methods, and computer readable media embodying such methods provide for allowing specification of per-ray clipping information that defines a sub-portion of a 3-D scene in which the ray should be traced. The clipping information can be specified as a clip distance from a ray origin, as an end value of a parametric ray definition, or alternatively the clipping information can be built into a definition of the ray to be traced. The clipping information can be used to check whether portions of an acceleration structure need to be traversed, as well as whether primitives should be tested for intersection. Other aspects include specifying a default object that can be returned as intersected when no primitive was intersected within the sub-portion defined for testing. Further aspects include allowing provision of flags interpretable by an intersection testing resource that control what the intersection testing resource does, and/or what information it reports after conclusion of testing of a ray.

Ray tracing using ray-specific clipping

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Method and apparatus for dynamic allocation of processing resources

Systems and methods include high throughput and/or parallelized ray/geometric shape intersection testing using intersection testing resources accepting and operating with block floating point data. Block floating point data sacrifices precision of scene location in ways that maintain precision where more beneficial, and allow reduced precision where beneficial. In particular, rays, acceleration structures, and primitives can be represented in a variety of block floating point formats, such that storage requirements for storing such data can be reduced. Hardware accelerated intersection testing can be provided with reduced sized math units, with reduced routing requirements. A driver for hardware accelerators can maintain full-precision versions of rays and primitives to allow reduced communication requirements for high throughput intersection testing in loosely coupled systems. Embodiments also can include using BFP formatted data in programmable test cells or more general purpose processing elements.

Apparatus and method for ray tracing with block floating point data

Ray tracing scenes is accomplished using a plurality of intersection testing resources coupled with a plurality of shading resources, communicative in the aggregate through links/queues. A queue from testing to shading comprises respective ray/primitive intersection indications, comprising a ray identifier. A queue from shading to testing comprises identifiers of new rays to be tested, wherein data defining the rays is separately stored in memories distributed among the intersection testing resources. Ray definition data can be retained in distributed memories until rays complete intersection testing, and be selected for testing multiple times based on ray identifier. A structure of acceleration shapes can be used. Packets of ray identifiers and shape data can be passed among the intersection testing resources, and each resource can test rays identified in the packet, and for which definition data is present in its memory. Test results for acceleration shapes are used to collect rays against acceleration shapes, and closest detection ray/primitive intersections are indicated by sending ray identifiers to shading resources.

Architectures for parallelized intersection testing and shading for ray-tracing rendering

A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions

A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.

Method and apparatus for accumulating floating point values

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Mountain View, CA, United States of America

Stephen C Purcell