Texas Instruments Corporation

Canon Kabushiki Kaisha

Stephen C Kwan

Taylor R Efland

Steven C Jones

Masanori Uchidoi

Hiroshi Aizawa

Yukio Mashimo

Yoshiyuki Takishima

Kenneth G Buss

Ross Eliot Teggatz

Andrew Marshall

Wayne T Chen

Subhashish Mukherjee

Bernhard H Andresen

Joseph A Devore

Fernando D Carvajal

Chin-Yu Tsai

Thomas A Schmidt

Robert C Martin

Norman L Culp

Frederick G Wall

An integrated SCR-LDMOS device (10) having a p+ region (13) in the drain region (12), but otherwise similar to a conventional LDMOS transistor. The device (10) may be implemented as a modification of a non-planar LDMOS (FIGS. 1 and 2). An alternate embodiment, device (30), may be implemented as a modification of a planar LDMOS (FIG. 3). In either case, the added p+ region (13, 37) provides the device (10, 30) with two parasitic bipolar transistors in an SCR configuration (FIGS. 4A and 4B).

Integrated SCR-LDMOS power device

An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.

Optimized power output clamping structure

A circuit (10) and method for protecting the gate-source elements of an FET includes a circuit (12, 13) for providing a pullup gate drive current to the gate-source elements. A voltage sensing circuit (45) senses a voltage on the gate-source elements to produce an indication if the voltage has exceeded a predetermined level. The voltage sensing circuit (45) has a zener diode (48) and a current mirror with first (52) and second (51) current flow paths. The zener diode (48) and the first flow path (52) are connected between the gate and a source of the FET. When a voltage between the gate and source of the FET exceeds the breakdown voltage of the zener diode (48) and one V.sub.gs in the current mirror, a current flows in the first flow path (52) producing a current flow in the second flow path (51). A circuit (20, 23, 62, 58, 60) reduces the pullup gate drive current in response to the current in the second flow path (51).

Method to protect gate-source elements of external power fETS from large

An LDMOS transistor (10) having a medium breakdown voltage and low Rsp includes a high voltage (n-) Nwell (38); a low voltage (n+) Nwell (42) formed in the high voltage Nwell (38); a drain region (64) formed in the low voltage Nwell (42); a Dwell (44) formed in the Nwell (70), the DWELL (46) including a p region (46) forming the backgate and a source region (48), a channel region (46a) defined between an edge of the source region (48) and an edge of the p region (46); and a gate (58) extending over the channel region (46a). Gate (58) extends onto a field oxide region (54) formed using a minimum photolithographic nitride opening to reduce the length of the drift region thus reducing Rsp. Rsp is also reduced by the addition of low voltage Nwell (42) to the drift region since low voltage Nwell (42) is more heavily doped than high voltage Nwell (38) thus reducing Rdson. The low voltage Nwell (42) added to the drift region also provides a reduction in breakdown voltage BV by increasing the field in the curvature region of the Dwell (46). Fabrication of transistor (10) is compatible with VLSI processes.

Medium voltage LDMOS device and method of fabrication

A bidirectional indicator driver circuit having automatic current sensing for driving an indicator regardless of its orientation. A comparator is coupled to memory which has an output indicating a driving direction polarity. An output driver which drives one terminal of a plurality of LED diodes is coupled to the memory. Individual three state buffers are coupled to the second terminal of each of the respective LEDs. The comparator detects whether the output driver is driving current. If no current is being driven to the LEDs, the comparator causes the memory to toggle states, and toggles the level of the polarity signal. Because the polarity signal is coupled to one terminal of the LEDs, the change in polarity will automatically cause one or more of the LEDs to be forward biased and emit light. The driver circuit can correctly operate LEDs which are incorrectly inserted into a circuit board or multichip module, because the direction the LEDs is driven will be changed until one or more devices is forward biased and current begins to flow. A second embodiment is described for an output driver circuit which will correctly operate LEDs regardless of their orientation using a clock and a common output driver. An integrated circuit incorporating the invention as output driver circuitry is described for use in a system where LEDs are used as indicators. Other devices, systems and methods are also disclosed.

Automatic bidirectional indicator driver

A circuit (10) and method for detecting a fault in a recirculation diode (13) in a switched power supply. The power supply has a switching transistor (12) that is turned on and off by a power supply control device (31), switchably applying a supply voltage (15) to an output (14). The recirculation diode (13) is connected between the output (14) and a reference potential (16). The circuit includes a sense resistor (11) in series between the supply voltage (15) and the switching transistor (12). A biasing element (25) is connected to clamp a current control element of the switching transistor (12) to the reference potential (16) when the switching transistor (12) is switched off so that a fault in the recirculation diode (13) results in a current flowing in the switching transistor (12). An amplifier (33) is connected across the sense resistor (11). The amplifier (33) has a variable gain (35) controlled by the power supply control device (31), a normal gain when the switching transistor (12) is turned on, but an increased gain when the switching transistor (12) would be normally turned off, to measure the current, if any, in the switching transistor (12) resulting from any faults in the recirculation diode (13). A control transistor (27) controlled by the power supply control device (31) is connected to switchably connect a voltage (30) to the current control element of the switching transistor (12).

Method and circuit for detecting faulty recirculation diode in a

An amplifier, preferably an integrated circuit, capable of accepting input common mode voltages below the circuit reference voltage or substrate voltage in the case of an integrated circuit. The amplifier comprises a differential voltage input having higher and lower voltage terminals, a first NMOS transistor coupled between a voltage supply and the higher voltage terminal and a second NMOS transistor coupled between the voltage supply and the lower voltage terminal. A third NMOS transistor is coupled between the voltage supply and the first transistor gate, a fourth NMOS transistor is coupled between the voltage supply and the second transistor gate and a sink resistor is coupled between the gate of the second transistor and the lower voltage terminal. A differential resistor is coupled between the gates of the first and second transistors. The first and second transistors include a source and a backgate coupled to each other and electrically isolated from the substrate with the source of each of the first and second transistors being coupled to a different one of the input terminals. The third and fourth transistors include a source and a backgate coupled to each other and electrically isolated from the substrate with the source of each of the third and fourth transistors coupled to opposite ends of the differential resistor. The circuit further includes a PMOS mirror circuit for providing an output.

MOS uni-directional, differential voltage amplifier capable of

A threshold detection circuit (10) is provided which comprises an input node (12) and an output node (14). The input node (12) is coupled to a current mirror (22) through a resistor (32). The current mirror (22) is further coupled to another current mirror (16), which is arranged to receive a reference current proportional to absolute temperature. The reference current is mirrored and, having been increased by a multiplier is received by a current sink (28). When the voltage level at the input node (12) exceeds a predetermined voltage threshold level, the current exceeding the amount sinkable by the current sink (28) is directed to the base of a switching transistor (30) coupled to the output node (14), and produces an output voltage level at the output node (14) indicative of the threshold voltage level being reached an/or exceeded at the input node (12). The predetermined threshold voltage may be at a level exceeding the circuit supply voltage level and is independent of ambient operating temperature.

Threshold detection circuit

An amplifier circuit (10) is provided which comprises a first transistor (12) and a second transistor (14). A current buffer circuit (16) is coupled to the basis of the transistors (12, 14) to provide base drive current. A voltage proportional to absolute temperature, V.sub.PTAT, is applied between the emitters of the transistors (12,14). An input current is received by the transistor (12) and an output current is generated by the transistor (14). The output current I.sub.out is amplified with respect to the input current I.sub.in by a gain factor which is substantially independent of temperature considerations. Circuitry is provided for altering the value of the voltage proportional to the absolute temperature, V.sub.PTAT, such that the gain of the amplifier circuit (10) is programmable.

Current amplifier circuit

A transient protection circuit comprising using a circuit connected to operate as a diode while presenting lower forward voltage drop for the same area and current as in pn junction diodes to provide greater efficiency. The circuit is a standard merged SCR circuit wherein a resistive path is provide between the base and collector of the pnp transistor and between the base and emitter of the npn transistor. In addition, there is provided a trip circuit wherein current is shunted away from the lateral transistor after a predetermined threshold current is passed through said transistor to minimize current drawn through the later transistor.

Transient protector

An analog circuit for implementing nonlinear operators such as an Nth-root extractor or an Nth-power operator. Two input currents yield one output current having the relationship I.sub.1 =I.sub.k.sup.-n I.sub.2.sup.n+2, where n is a positive integer and I.sub.k is a gain setting current. When n=1 the circuit functions as a square root extractor or a squaring converter. The present circuit is readily implemented with bipolar technology and offers high speed performance and temperature stability without external compensation. Typical applications of the present circuit include RMS measurement, auto-correlation, power measurement and gain compression/expansion.

Nth Order function converter

Current sensing circuits especially adapted for use with either capacitive touch plate or mechanical switch keys. The circuits include a transistor whose base is connected to a constant voltage source and whose emitter-collector circuit is connected between the touch plate or switch keys and an input to a comparator. A second transistor and a capacitor are interconnected with the first transistor to provide transient surge protection. The circuits distinguish between differing values of current and activate the comparator which produces a signal indicative of the existing condition.

Current sensing of capacitive keyboard arrays

A camera detects which of a number of operating modes is dialed into a flash unit by sensing the current level produced by a source. In response to dialing of a daylight EE mode, the camera measures the brightness of the object to be photographed and conforms the diaphragm aperture to a preselected shutter speed. In one flash mode the flash unit transmits desired aperture and shutter speed data suitable for flash and the camera automatically responds. In another mode, the shutter speed is set into the camera and the camera automatically controls the diaphragm aperture on the basis of data transmitted by the flash unit.

Photographic mode selector system

A storage device for storing photographic exposure information employs a closed-loop analog-to-digital (A-D) converter circuit includes a counter and a digital-to-analog (D-A) converter. The influence of erroneous signals which are created at the output of the D-A converter when the exposure information is stored in the counter is eliminated. The D-A converter circuit employs a ladder network of coarse accuracy. The stored exposure value, however, is highly accurate because of the closed-loop nature of the A-D converter circuit. Means responsive to the stored value for operating the exposure system of the camera are disclosed.

Exposure information storage device for a photographic camera

A differential reference voltage regulator for I.sup.2 L silicon integrated circuits having temperature compensation means including a temperature reference transistor and a balance resistance, R2, connected in series between a reference resistance, R1, and a current source transistor wherein ##EQU1## where n is the ratio of currents applied to a pair of transistors which form a differential regulator.

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Plano, TX, United States of America

Stephen C Kwan