Advanced Micro Devices Corporation

Intrinsity, Inc.

Evsx, Inc.

Apple Inc.

Stephen C Horne

James S Blomgren

Michael R Seningen

Terence M Potter

Anthony M Petro

John Christian Holst

Raymond T Lee

Asim A Selcuk

Nicholas John Kepler

Christopher A Spence

Richard K Klein

Craig S Sander

Scott H McMahon

Brian D McMinn

Rich K Klein

James M Buchanan

Donald W Glowka

Gopal Vijayan

Christoper A Spence

Edward Martin McCombs, Jr

Seungyoon P Song

David W Chrudimsky

Daniel C Chow

Gopi Ganapathy

Raghuram S Tupuri

Kenneth D Amstutz

Alexander E Runas

A method performed by a tablet device having a touch screen display and at least one sensor coupled to a processor includes using the at least one sensor to determine that a cover attached to the tablet device is in a partially open configuration, receiving a touch input gesture from an uncovered portion of the touch screen display when the cover is in the partially open configuration, identifying, based upon a type of the input gesture, an operating parameter of the device, determining, based upon the input gesture, a setting value for the operating parameter, and altering the operating parameter of the device based upon the setting value. For example, the gesture can be a swipe, the operating parameter can be a brightness of the display, and altering the operating parameter can include adjusting the brightness of the display based upon the value.

Device input modes with corresponding cover configurations

A mechanism for protecting integrated circuits (IC) from security attacks includes an IC having components that may store one or more data items and may perform a number of functions and which produce resulting events. The IC may also include a security module that may modify signals and events provided to the components such that the resulting events are modified in a non-effectual way but that causes the events to be non-deterministic relative to an event that is external to the integrated circuit when the resulting events are viewed externally to the IC. This may result in obscuring the data, and the functions from being observed from external to the IC, particularly when using an IR laser probe.

Mechanism for protecting integrated circuits from security attacks

A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

Memory including a reduced leakage wordline driver

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Minimizing transistor size in integrated circuits

The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Method and apparatus for a 1 of N signal

A method and apparatus for random-access scan of a network of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates ( ) driven by multiple overlapping clock signals generated from a clock generation circuit ( ) coupled to a clock spine ( ). Each clocked precharge logic gate and each scan gate include a logic tree ( ) with one or more evaluate nodes, a precharge circuit ( ), an evaluate circuit ( ), and one or more output buffers ( ). Each scan gate further includes a scan circuit ( ) that accepts scan control signals ( , and ) and couples to one or more scan registers ( ) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Dynamic logic scan gate method and apparatus

This invention discloses a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool includes a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool . The routing rule generation tool further includes a noise sensitivity/gate characterization tool and a rule generator tool . The block build tool further includes a gate sizing tool , a gate analysis tool , a route rule selecting tool , a route assigning tool

Generation of route rules

A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Method and apparatus for a N-NARY logic circuit using capacitance isolation

The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer , a levelizer , a backward logic scanner , a forward logic scanner , a gate target delay incrementor , and a gate target delay comparator that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Method for calculating dynamic logic block propagation delay targets using time borrowing

A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers. Scan control signals and scan timing signals also operate to force the output buffers of the scan gate to a preselected level, which then propagates through the network to create an output state on the next scan gate in the network, which can then be read and compared to an expected output state given the output state of the previous scan gate.

Method and apparatus for scan of synchronized dynamic logic using embedded scan gates

The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.

Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state

The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Method and apparatus for generating clock signals

The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate. The phase of an individual local clock signal overlaps an earlier phase local clock signal by an amount approximately equal to the overlap of the phase of the next individual local clock signal. The first dynamic logic gate, the intermediate dynamic logic gate(s), and the last dynamic logic gates couple such that an individual dynamic logic gate with an individual local clock signal and phase may only provide a signal to the next individual dynamic logic gate that uses a next phase local clock signal where the gates may couple together in series, in a feed back loop, or a feed forward loop.

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Austin, TX, United States of America

Stephen C Horne