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Ati Technologies Ulc

Stephen C Hale

Stephen C Purcell

Korbin S Van Dyke

Nital P Patwa

Parin Bhadrik Dalal

Chad Edward Fogg

Niteen Aravind Patkar

Sanjay Mansingh

Dee Tovey

An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Variable-length code decoder

An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.

Method and apparatus of configurable processing

A multiplier carry bit compression apparatus and method for a multiplier using Wallace tree addition structures uses a plurality of early and late carry bit compression operations for each level of the Wallace tree addition structure. For each level in a Wallace tree addition structure, each early carry bit compression operation compresses early compression bits prior to each corresponding late carry bit compression operation that compresses late carry bits.

Multiplier carry bit compression apparatus and method

The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor includes a first carry-propagate adder that adds a lower 16 bits of a constant or displacement and a lower 16 bits of a segment base, and a second carry-propagate adder connected to the first carry-propagate adder, wherein the second carry-propagate adder adds a lower 16 bits of a base and an output of the first 16-bit carry-propagate adder to generate a lower 16 bits of an address. In one embodiment, the first carry-propagate adder and the second carry-propagate adder are each 16-bit carry-propagate adders.

Apparatus and a method for address generation

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San Jose, CA, United States of America

Stephen C Hale