Texas Instruments Corporation

Stephen Busch

Hamid Rahim Sheikh

William M Johnson

Shashank Dabral

Serge Bernard Lasserre

John W Glotzbach

Denis R Beaudoin

Jeffrey L Nye

Shalini Gupta

David Harold Bartley

Murali S Chinnakonda

Ajay Jayaraj

Toshio Nagata

Frederic Jean Noraz

Marouane Berrada

Robert Jp Nychka

Ganesh Sundararajan

Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured 'on the fly' to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Integrated circuit with control node circuitry and processing circuitry

A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.

Master circuits having dynamic priority leads coupled with memory controller

An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction.

System and method for maintaining maximum input rate while up-scaling an image vertically

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Grasse, France

Stephen Busch