Sun Microsystems, Inc.

Stephen Berry

Mark W Insley

Jay C Robinson

The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An electric circuit of the present invention has one-hundred-twenty pins along the length of the housing. The housing of the memory device has a length of approximately 85.6 mm and a width of approximately 54.0 mm. The left and right side socket interface portions of the housing have a minimum width of approximately 3.3 mm. The top socket interface portion has a maximum thickness of approximately 3.5 mm and a minimum height of approximately 3.0 mm. The bottom socket interface portion has a maximum thickness of approximately 5.0 mm and a minimum height of approximately 10.5 mm. Furthermore, the memory device interface portion of the present invention includes at least one pin which provides access to an address signal which indicates a memory array address location within the memory device. The interface portion also includes at least one pin which provides access to a data signal. Additionally, the interface portion includes a row address strobe signal which indicates that the address signal provided to the memory device is a row address, similarly at least one pin providing access to a column address strobe signal is included in the interface portion of the present invention. This column address strobe signal indicates that the address signal provided to the memory device is a column address. Further, at least one pin providing access to a memory write signal and at least one pin providing access to a memory output enable signal are included in the interface portion. Finally, the memory device interface of the present invention provides access to a power supply and to ground.

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Littleton, MA, United States of America

Stephen Berry