Semiconductor Insights Inc.

Jason Abt

Edward Keyes

Stephen Begg

Val Gont

Mohammed Ouali

Dale Mcintyre

Vyacheslav L. Zavadsky

Elmehdi Aitnouri

Vyacheslav L Zavadsky

Dale McIntyre

Thomas Kapler

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Method of design analysis of existing integrated circuits

The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.

Method and apparatus for reducing redundant data in a layout data structure

The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.

Method and apparatus for locating short circuit faults in an integrated circuit layout

A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre-existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format data, horizontally and vertically aligning the vector format data of the electronic stored images of the physical IC layers, and providing a multi-layer display of the aligned vector format data. A net-list or schematic is generated from the multi-layer display of the vector format data. The net-list and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks. The vector format data may be altered to correct errors in the images or manipulated to correct the alignment of the images. In addition, the schematic may be traced to the image of the physical IC layer.

Computer aided method of circuit extraction

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Stephen Begg