Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Eidetic Communications Inc.

Microsemi Solutions (us), Inc.

Aquantia Corporation

Maxlinear Asia Singapore Pte Ltd

IP Gem Group, LLC

Stephen Bates

Peter Graumann

Philip Lyon Northcott

Saeed Fouladi Fard

Sean Gregory Gibb

Rino Micheloni

Alessia Marelli

Ognjen B Katic

Peter John Waldemar Graumann

Phil Northcott

Hossein Sederat

Oren Berman

Rahul Advani

A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.

Apparatus and method for encrypting data in a data storage system

A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.

System and method for performing erasure coding in a distributed storage system

A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.

System and method for performing computational storage utilizing a hardware accelerator

A method and system for transferring NVMe data over a network comprises using a discrete buffer memory device to generate a write command from an NVMe-over-RDMA write command request, store the user data from a client host of the network, and send an interrupt signal to a NVMe storage device of the network. The NVMe storage device retrieves the write command from the discrete buffer memory device and performs a direct memory access transfer of the stored user data from the discrete buffer memory device to the NVMe storage device. The discrete buffer memory device comprises a controller and a random access memory for generating commands and storing the commands in a submission queue of the random access memory. The controller can clear commands from the submission queue based on completion commands received in a completion queue of the random access memory.

Apparatus and method for transferring data and commands in a memory management environment

A system, device and method are provided for command processing for a fast block input/output (I/O) device, such as a solid state hard drive (SSD). A bridge device is directly connected to the fast block I/O device and configured to intercept a command sent from a controller to the fast block I/O device and to process the command within the bridge device. The bridge device can process the command independent of interaction with the controller. Processing the command can include copying or moving data, performing protocol translation, performing data manipulation, or performing near-data processing, including performing a context-aware service. Near-data processing comprises processing the command within the bridge device, instead of on the fast block I/O device or the controller, which provides advantages of in-situ processing without the limitations associated with processing performance on the fast block I/O device.

Apparatus and method for command processing for a fast block input/output device

A solid-state storage device (SSD) controller is provided for use with an SSD. The SSD includes a plurality of memory cells, such as non-volatile memory (NVM) cells. The SSD controller comprises a processor and a memory storing statements and instructions for execution by the processor to perform a method of configuring the memory cells. In a dynamic configuration implementation in which at least a subset of the NVM cells are configured in a first bit retention mode, the method includes: monitoring data activity in relation to the SSD; and dynamically reconfiguring the subset of the NVM cells in a second bit retention mode based on the monitored data activity, such as whether data traffic comprises a majority of read activity or write activity. In a static configuration implementation, the method includes receiving at least one performance characteristic for the NVM cells; and configuring the subset of the NVM cells in a first bit retention mode based on the received at least one performance characteristic.

Method of configuring memory cells in a solid state drive based on read/write activity and controller therefor

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.

Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction

A method is disclosed for setting or modifying a threshold voltage in a NAND flash memory, using an optimization method and based on an error, such as stored in a threshold voltage table. In an embodiment, a method is provided to optimize the read voltage on a NAND flash memory in order to minimize the errors on the NAND flash memory in the fewest reads operations as possible. Advantageously, the method of the present disclosure is more reliability as the method minimizes a Raw Bit Error Rate (RBER) on the NAND flash memory. In an embodiment, a NAND controller adjusts an existing cell read threshold voltage for a selected cell, using an iterative optimization method, based on a difference between first and second error rates, or a difference between first and second probabilities, to generate an adjusted cell read threshold voltage.

Threshold voltage adjustment in solid state memory

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Systems and methods for reclaiming memory for solid-state memory

A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

Method and system for decoding encoded data stored in a non-volatile memory

A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

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Canmore, Canada

Stephen Bates