Texas Instruments Corporation

Stephen Arion Meisner

Scott Robert Summerfelt

John Britton Robbins

Bhaskar Srinivasan

Scott William Jessen

Guruvayurappan Mathur

Poornika Fernandes

Anthony DiCarlo

David Matthew Curran

Shih Chang Chang

Russell Duane Fields

Thomas Terrance Lynch

In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Integrated circuits having dielectric layers including an anti-reflective coating

An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer

An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Alignment mark for opaque layer

The present invention provides a method for manufacturing a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device may include providing a material stack, the material stack including a spacer layer having one or more openings therein and located over control circuitry located on or in a semiconductor substrate, a layer of hinge material located over the spacer layer and within the one or more openings, and a layer of hinge support material located over the layer of hinge material and within the one or more openings. The method may further include patterning the layer of hinge support material using photoresist, patterning the layer of hinge material using the patterned layer of hinge support material as a hardmask, and removing the patterned layer of hinge support material from over an upper surface of the patterned layer of hinge material.

Unique method for manufacturing a digital micromirror device and a method for manufacturing a projection display system using the same

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Allen, TX, United States of America

Stephen Arion Meisner