Intel Corporation

Stephen Anthony Fischer

Sanjeev S Jahagirdar

Varghese George

Alon Naveh

Subramaniam M Maiyuran

Alexander D Peleg

Larry M Mennemeier

Carole Dulong

Eiichi Kowashi

Salvador Palanca

Shai Rotem

Robert Milstrey

John B Conrad

Shekoufeh Qawami

Stephen H Gunther

Bruce A Young

Kirk D Brannock

Yuriy Bulygin

Kevin Gotze

Jason W Brandt

Norman J Rasmussen

Jeffrey L Rabe

Dave Carson

Bret L Toll

Millind Mittal

Eliezer Weissmann

Martin Guy Dixon

Benny Eitan

Andrew J Herdrich

Shreekant S Thakkar

James A Sutton, Ii

Michael J Allen

Dheeraj R Subbareddy

Inder M Sodhi

Eugene Gorbatov

David A Koufaty

Michael Mishaeli

Patrice L Roussel

Ganapati Srinivasa

Ashish V Choubal

Andrew D Henroid

David Johnston

George W Cox

Scott D Hahn

Hisham Shafi

Rinat Rappoport

Paolo L Narvaez

Richard D Pashley

Gaurav Khanna

Mishali Naik

Paul Brett

David R Gray

Tuan H Bui

Joseph D Schutz

Charles H Lucas

Abirami Prabhakaran

Oron Lenz

Patrick P Gelsinger

Babak Sabi

Stephen F Sullivan

David J Shield

Sanjeev S Sahagirdar

Stuart T Hopkins

Gregory K Crain

Benny Maytal

Gilbert A Neiger

Glenn J Hinton

Shay Gueron

Andrew V Anderson

Jesse R Walker

Steven M Bennett

Ernie F Brickell

Howard C Herbert

James B Crossland

Dion Rodgers

Russell Jerome Fenger

Bryant E Bigbee

Gideon Gerzon

Douglas Raymond Moran

Leena K Puthiyedath

Thomas R Huff

James S Coke

Shamanna M Datta

Randolph L Campbell

Thomas F Heil

Charles E Dike

Frederick J Pollack

Edward V Gamsaragan

Eric R Heit

Jeff L Rabe

Robert R Sullivan

Erez Carmel

William C Alexander, Iii

George Varghese

Alon Navch

Russel J Fenger

Gerald Bennett

Vladimir Pentovski

Gustay Laub, Iii

Gustav Laub, Iii

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.

Protection against return oriented programming attacks

In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.

Detection of return oriented programming attacks

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Method and apparatus for a zero voltage processor sleep state

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

MFENCE and LFENCE micro-architectural implementation method and system

A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.

Method and apparatus for a non-deterministic random bit generator (NRBG)

Method and apparatus for a zero voltage processor

Growing community of inventors

Gold River, CA, United States of America

Stephen Anthony Fischer