Broadcom Corporation

Rf Micro Devices, Inc.

Zeevo, Inc.

Mstar Semiconductor, Inc.

Globalfoundries Inc.

Integrated Device Technology, Inc.

Telencomm, Inc.

Stephen Allott

Thomas Gregory Mckay

Iain Butler

Thomas G McKay

Jonathan Gowing

Cyril Valadon

Julian Jenkins

Edwin X Li

Louis Pandula

Mark Alexander John Moffat

A pulsed radar system is presented that includes a sliding window and DC offset. A method of pulsed DC radar operation, comprising an operation state, the operation state including initializing parameters for a current integration window; providing timing for the current integration window to an integrating filter based from a transmit pulse; providing a DC offset associated with the current integration window; and incrementing the current integration window to the next integration window to be timed from a next transmit pulse.

Sliding window and DC offset correction technique for pulse doppler radar systems

The present disclosure relates to an injection locked oscillator system and processes and, more particularly, to structures and processes for generating an inductor-less frequency multiplier using injection locking and histogram calibration with a back-gate process. The structure includes injection locked oscillator (ILO) system which is structured to provide a local oscillator (LO) and a Digitally Controlled Oscillator (DCO) or Voltage Controlled Oscillator (VCO) frequency which is not harmonically related by an integer multiple to an output frequency.

Injection locked oscillator system and processes

One aspect of the present invention includes a radio frequency (RF) receiver having a first mixer and a second mixer. The first mixer may be an I-mixer and the second mixer a Q-mixer for downconverting the received RF signal. An impedance circuit is disposed between the first mixer and the second mixer to decouple the channels. In another aspect of present invention, the RF receiver includes a digital filter having at least one complex coefficient. The digital filter exhibits asymmetrical frequency response, and may be used to compensate the asymmetrical frequency response of another filter in the RF receiver.

Multimode receiver with complex filter

Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a poly phase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response.

Discrete time polyphase mixer

A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.

Non-overlapping clock generator

Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a polyphase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response.

An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Split source RF MOSFET device

A method and apparatus for determining a delay vector from inputs of in-phase and quadrature phase low pass filters to an output of the demodulator of a dual mixer radio receiver and from such delay measurement computing and providing DC offset correction to said receiver.

DC offset correction for use in a radio architecture

The present invention is a differential transconductance amplifier circuit that includes matched cross-coupled transconductance elements connected such that the differential gain of the amplifier is determined by only passive elements. By virtually eliminating the effects of active elements on the amplifier gain, the amplifier operates in a very linear manner over its entire operating range. Power consumption, amplifier noise level, and dynamic range can be optimized with appropriate selection of the passive elements that determine amplifier gain.

High linearity differential transconductance amplifier

A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator element including a plurality of current sources interconnected to provide output transconductance voltages, and a variable load for the current sources including first and second load resistors each serially connected with one other plurality of current sources. A variable resistance interconnects nodes of the load resistors with the variable resistance comprising a pair of native MOS transistors having low threshold voltages. In a preferred embodiment the first and second load resistors comprise first and second MOS transistors with the pair of native transistors serially connected between source elements of the first and second MOS transistors.

Transconductance device employing native MOS transistors

A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.

Analog hold cell in a CMOS process

Methods and apparatus of amplifying signals. One method includes receiving a variable power supply, generating a variable bias current, and applying the bias current to a load such that an average output voltage is generated. The method further includes receiving an input signal, generating a current proportional to the input signal, and subtracting the current from the variable bias current. As the variable power supply changes value by a first amount, the variable bias current is varied such that the average output voltage varies by the first amount.

Logarithmic IF amplifier with dynamic large signal bias circuit

An analog memory cell that may be incorporated into a low power oscillator is provided. The analog memory cell stores an analog voltage as a digital signal and converts the digital signal back to an analog voltage to allow continued generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the analog memory cell in the low power oscillator is fully implementable in a CMOS process.

Analog memory cell in a low power oscillator

An automatic gain control circuit for amplifying an input signal of varying strength and having a fast attack mode of operation and a tracking mode of operation includes a gain controlled amplifier for receiving the input signal and producing an amplified analog output signal, a receive signal strength indicator (RSSI) circuit for receiving the amplified analog signal and producing an output voltage indicative of strength of the signal, and decision logic circuitry responsive to the output voltage from the RSSI circuit for controlling gain to the gain controlled amplifier. A plurality of comparators is provided for comparing the output voltage from the RSSI circuit to threshold voltages in generating output signals indicative of the voltage comparisons which can indicate the RSSI output voltage being very low, low, high, or very high as inputs to the decision logic circuit. The decision logic circuitry can then provide a fast acquisition mode of operation or a tracking mode of operation depending on the output signals from the plurality of comparators. In preferred embodiments, the gain controlled amplifier can comprise a plurality of cascaded gain controlled amplifier circuits with the gains of the cascaded gain control amplifier circuits being controlled by the decision logic circuitry. The threshold voltages provided to the plurality of comparators can be programmable for specific modes of operation.

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Scotts Valley, CA, United States of America

Stephen Allott