Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

Stephen Alan Chessin

Charles E Narad

Yousef A Khalidi

Madhusudhan Talluri

Michael Steven Walker

Shing I Kong

Louis Yonlo Tsien

Rodrick Ison Evans

Glen R Anderson

Blake Alan Jones

Tarik Pertev Soydan

Tarik P Soydan

A method for managing a corrupted memory block. The method includes detecting the corrupted memory block, and removing, after detecting the corrupted memory block, references to the corrupted memory block. The method further includes identifying, after detecting the corrupted memory block, an uncorrupted memory block and analyzing each cache line. The method further includes determining, while analyzing each cache line, that a first cache line includes an uncorrectable error and creating, based on determining the first cache line includes the uncorrectable error, a second cache line including an artificial error, and migrating the second cache line to the uncorrupted memory block, where a layout of the corrupted memory block is maintained.

Memory error propagation for faster error recovery

A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.

Prediction and prevention of uncorrectable memory errors

One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory location in a main memory by a first processor, wherein the correctable error is detected by error detection and correction circuitry. Next, the system reads tag bits for a cache line associated with the memory location, wherein the tag bits contain address information for the cache line, as well as state information indicating a coherency protocol state for the cache line. The system then tests the memory location by causing the first processor to perform read and write operations to the memory location to produce test results. Finally, the system uses the test results and the tag bits to determine the cause of the correctable error, if possible.

Method and apparatus for classifying memory errors

A system, method and computer program product for compiling a source file and to generate a unitary data structure (UDS) containing information relating to symbols and associated global registers. The UDS permits assessment of symbol conflicts for global registers. The compiler also generates object files from related source files. The object files include the global symbol information relating to particular global registers, to enable diagnosis of conflicts between global symbols and registers.

Unitary data structure systems, methods, and computer program products, for global conflict determination

A system, method and computer program product for compiling and linking a source file and to generate a symbol table associating a global symbol with a register referenced in the source file. The symbol table enables a linker to initialize the global registers using a relocation entry which holds an initializer. The compiler also generates an object file from the source file. The object file includes the global symbol information. A linker links the object file potentially with at least one other object file or shared library to thereby generate an executable file or shared library. The linker uses the global symbol information contained in the object file to initialize the global registers and to perform relocation operations.

Method and system for compiling and linking source files

A system, method and computer program product for compiling a source file and to generate a data structure associating a global symbol with a global register referenced in the source file. The data structure enables a linker to initialize the global registers. The compiler also generates an object file from the source file. The object file includes the global register information. A linker links the object file potentially with at least one other object file or shared library to thereby generate an executable file or shared library. The linker uses the global symbol information contained in the object file to initialize the global registers and to perform relocation operations.

Methods, computer program products, and apparatus for initializing

A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible page sizes where L is a positive integer greater than one. Each of the L different page sizes is selected to be a test page size and a test is performed. During the test, a pointer into a translation storage buffer is calculated. The pointer is calculated from the virtual address to be translated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The pointer points to a candidate translation table entry of the translation storage buffer. The candidate translation table entry has a candidate tag and candidate data. The candidate tag identifies a particular virtual address and the candidate data identifies a particular physical address corresponding to the particular virtual address. A virtual address target tag is extracted from the virtual address to be translated. The virtual address target tag is calculated by assuming that the virtual address to be translated corresponds to a mapping of the test page size. The target tag and the candidate tag are then compared. If the target tag matches the candidate tag, the candidate data is provided as the physical address translation corresponding to the virtual address to be translated.

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Mountain View, CA, United States of America

Stephen Alan Chessin