Cirrus Logic Inc.

Stephen A Smith

Bryan Michael Richter

Daniel G Bezzant

Arunachalam Vaidyanathan

Kasturiraman Gopalaswamy

Dave M Singhal

Narasimha R Nookala

Jihad Y Abudayyeh

Suhas Anand Shetty

Ashutosh S Dikshit

Jafar Naji

Sriram Ramamurthy

Abdul Q Kashmiri

Jerry L Clark

Mike Assar

Kaushik L Popat

Puducode S Narayanan

Sanjiv D Pathak

John E Stone, Iii

Reza G Omid

A method and apparatus for maintaining the voltage level of data signals supplied to an integrated circuit, such as a PCMCIA card, at the same level as power also provided to the integrated circuit. Circuitry for maintaining the voltages at the same level is preferably embodied within a system having a card controller integrated circuit, a power supply, and a peripheral card socket for receiving a removable PCMCIA card. The power supply is controlled by the card controller to provide power to the PCMCIA card through the card socket at a voltage level matching internal voltage requirements of the PCMCIA card. The card controller is connected directly to the PCMCIA card by a signal transmission line. Circuitry is provided for ensuring that the voltage of data signals transmitted along the data bus line to the PCMCIA card substantially match the voltage of power provided from the power supply to the PCMCIA card along a power supply line. In this manner, damage resulting from a power mismatch within the PCMCIA card is avoided.

Computer system host adapter for controlling signal levels to peripheral

A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus. If the system bus does not have DMA capability then the DMA controller and the bus master work to disable the CPU and take control of the system bus during a DMA data transfer. The DMA controller then controls the transfer of data between the peripheral and the internal system memory.

PCMCIA host adapter and method for variable data transfers

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

Method and apparatus for interfacing between peripherals of multiple

An integrated circuit allows a user or system designer to program the length of a transaction cycle by programming the lengths of the setup time period, the command time period and the recovery time period, individually. An eight-bit register is used to store a two-bit prescaler value and a six-bit count value for each of the setup, command and recovery time periods. The value represented by the prescaler is then multiplied by the count value and the resulting value is input to a timer which counts down from the resulting value, signalling to a state machine when it has reached zero. A four-state state machine sends the command to begin each transaction cycle and each setup, command and recovery time period within each transaction cycle. The state machine is notified by the timer when the time period has elapsed for each of the three states so that it can send the signal to begin the next state. At the beginning of each command time period, the state machine also signals to the system that the command can be executed. At the beginning of each transaction cycle the state machine also sends the signal to load the next data value and address value from the first-in first-out stack onto the data and address busses, respectively.

Apparatus and method for programming the setup, command and recovery

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.

Method and apparatus for providing register and interrupt compatibility

A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrangement further includes a third device for pulling the common terminal to the second voltage at all times. The third device supplies a current to the common terminal that is either equal to or less than the current supplied by the second device.

Wired combinational logic circuit with pullup and pulldown devices

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.

Method and apparatus for providing register compatibility between

A method and apparatus for monitoring and controlling power to a device such as a PCMCIA/PC card. A PCMCIA/PC card adapter is provided for communicating data and control signals to and from a PCMCIA/PC card and a host processor. The PCMCIA/PC card adapter may communicate with the PCMCIA/PC card to determine the correct voltage(s) for the PCMCIA/PC card. The PCMCIA/PC card may then communicate instruct a power control circuit to provide an appropriate voltage to the PCMCIA/PC card. The power control circuit may be provided with status monitoring registers containing status data reflecting monitored conditions of the PCMCIA/PC card and power supply. A System Management Bus (SMB) may link the power control circuit and the PCMCIA/PC card adapter. If an abnormal status is detected in the PCMCIA/PC card or power supply (e.g., over temperature, over current, thermal shutdown, or the like) the power control circuit, provided with an arbiter and SMB master state machine, may assert control of the SMB and transfer contents of the status registers to corresponding status registers in the PCMCIA/PC card adapter. If abnormal status is detect in the status registers of the PCMCIA/PC card adapter, the PCMCIA/PC card adapter may instruct the power control circuit to shut down power to the PCMCIA/PC card. The PMCIA/PC card adapter may further generate and transmit an interrupt signal to a host processor.

Apparatus and method for reading back socket power status information

A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers. The index registers of the PC card controllers are updated when the processor writes to an I/O address, without acknowledging the write on the PCI bus. This allows the writes to propagate through the system to lower levels, instead of being stopped by a subtractive decode device. To perform this, each PC card controller compares the socket pointer information with the updated index in the index register. When at least a portion of the socket pointer information matches at least a portion of the updated index, the PC card controller updates with write data the data register pointed to by the index register.

Computer system with multiple PC card controllers and a method of

A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.

Selective low power clocking apparatus and method

A device for use in a computer system, particularly a personal computer (PC) which provides compatibility for a proposed ISA plug and play (PNP) standard. The device of the present invention is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.

Backward compatibility for plug and play systems

A computer system including one or more PCMCIA expansion slots allows video and/or audio capabilities to be added to the system through a standard PCMCIA interface, utilizing multimedia type PCMCIA peripheral cards. A PCMCIA host adapter integrated circuit interrogates a PCMCIA peripheral card to determine whether or not the PCMCIA peripheral card is a multimedia type PCMCIA peripheral including video or audio capability. If the PCMCIA peripheral card is a multimedia type peripheral, the PCMCIA host adapter integrated circuit couples the PCMCIA peripheral card directly to the graphics and sound controller integrated circuits, using the standard PCMCIA interface and bypassing the host system bus. Otherwise, if the PCMCIA peripheral card is a standard PCMCIA peripheral, then the PCMCIA host adapter integrated circuit interfaces communications between the PCMCIA peripheral card and the host system bus in a conventional manner. The computer system includes a multi-windowing or display function whereby a typical computer applications program may be operating and displayed in a first window or display while the system simultaneously displays a playback or live video signal from a multimedia type peripheral card in a second window or display.

Adapter for detecting whether a peripheral is standard or multimedia

A peripheral device capable of generating interrupt request signals compliant with the Industry Standard Architecture (ISA) protocol, and the Peripheral Component Interconnect (PCI) protocol. The peripheral device comprises a signal generator block which selectively generates either the interrupt request signals of the PCI protocol or a set of bits representative of interrupt request signals of the ISA protocol. The set of bits are transferred serially to a converter circuit which generates the interrupt request signals of the ISA protocol based on the bits. The signal generator block generates bits in such a way as to support both pulse mode and level mode interrupt request signals for the ISA protocol.

Apparatus and method for supporting multiple interrupt protocols with

A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

Growing community of inventors

Palo Alto, CA, United States of America

Stephen A Smith