American Semiconductor Corporation

International Business Machines Corporation

University of California

Boise State University

Stephen A Parke

Douglas R Hackler, Sr

Jack Allan Mandelman

Matthew R Wordeman

John Anthony Bracchitta

Jeffrey P Gambino

Kelly James DeGregorio

Chenming Hu

Badih El-Kareh

Ping Keung Ko

Dale G Wilson

Richard Alan Hayhurst

Fariborz Assaderaghi

A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.

Double-gated sensor cell

Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.

Independently-double-gated transistor memory (IDGM)

A family of logic circuits is constructed from double-gated four terminal transistors having independent gate control. First and second inputs to each logic element are independently coupled to the top and bottom gates of a transistor. The output voltage developed at either the source or drain represents an output logic state value according to the designed logic element. In a dynamic configuration the drain is precharged to an appropriate voltage. Complementary static CMOS configurations are also shown. Bottom Gates not driven by logic inputs or control signals may be biased to control the speed and power of the described logic circuits. Specific designs are given for AND, NAND, XOR, XNOR, OR and NOR combinational logic elements.

Independently-double-gated combinational logic

This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.

Independently-double-gated field effect transistor

An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Double-gated transistor circuit

A double-gated transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain.

Multi-configurable independently multi-gated MOSFET

A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.

SRAM cell

This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.

Damascene double gated transistors and related manufacturing methods

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N and P diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N diffusion to said P diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P diffusion is formed in the N well in the pillar adjacent the distal end and a N diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

Method for forming pillar CMOS

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N,and P,diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N,diffusion to said P,diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P,diffusion is formed in the N well in the pillar adjacent the distal end and a N,diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

Pillar CMOS structure

According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N&plus; and P&plus; diffusions. This fabrication process results in a pillar structure which has an n&plus; diffusion contacting a portion of the base of the transistor body and a P&plus; diffusion contacting the remainder of the base of the transistor body. The proportion of N&plus; and P&plus; area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.

Pillar transistor incorporating a body contact

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N.sup.+ and P.sup.+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N.sup.+ diffusion to said P.sup.+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P.sup.+ diffusion is formed in the N well in the pillar adjacent the distal end and a N.sup.+ diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.

According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.

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Nampa, ID, United States of America

Stephen A Parke