International Business Machines Corporation

Stephen A Mongeon

Jeffrey P Gambino

Anthony C Speranza

William R Tonti

Dale P Hallock

Robert O Frenette

Jed Hickory Rankin

James William Adkisson

Mark David Jaffe

Robert K Leidy

Richard John Rassel

John Anthony Bracchitta

Leah M P Pastel

Walter Victor Lepuschenko

David Alan Meatyard

Gabriel Hartstein

MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.

MEMS switches and fabrication methods

MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to be deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.

Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Random personalization of chips during fabrication

A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits.

Method of making small geometry features

A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.

Dual work function CMOS device

Method for producing dual work function CMOS device

A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal doped layer. The nitride layer is etched, with the etch stopping on the conformal doped layer, thereby forming nitride spacers. Deep source and drain regions are formed by either ion implantation or diffusion. The device is then heat treated so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region. The method is applicable to N-substrate (P-channel), P-substrate (N-channel), and complementary metal oxide semiconductor (CMOS) devices.

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Essex Junction, VT, United States of America

Stephen A Mongeon