Vidiator Enterprises Inc.

Redrock Semiconductor, Inc.

Luxxon Corporation

Stephen A Molloy

Roger Khemraj Brooks

Dave M Singhal

Yanda Ma

Qing Zhang

Chi-Te Feng

Tao Lin

A method for forming an output stream of data includes determining an output resolution for the output stream of data, determining an output frame rate for the output stream of data, determining an output color depth for the output stream of data, retrieving a first frame of data, a second frame of data, and a third frame of data from an input stream of data, the input stream of data having an input resolution, an input frame rate, and an input color depth, subsampling the first frame of data, the second frame of data, and the third frame of data to respectively form a first subsampled frame of data, a second subsampled frame of data, and a third subsampled frame of data, when the output resolution is lower than the input resolution, dropping the second subsampled frame of data, when the output frame rate is lower than the input frame rate, reducing color depth for the first subsampled frame of data and the second subsampled frame of data to respectively form a first reduced frame of data and a second reduced frame of data, when the output color depth is smaller than the input color depth, and converting the first reduced frame of data and the second reduced frame of data into the output stream of data.

Methods for transforming streaming video data

According to one embodiment, a circuit configured to form an output video stream includes a resolution modification circuit configured to receive a plurality of video frames from a frame buffer, and configured to modify resolution of the plurality of video frames, when the desired resolution for the output video stream is different than a resolution of the input video stream, the plurality of frames of data derived from an input video stream, a frame reducing circuit coupled to the resolution reducing circuit configured to reduce a number of video frames in the plurality of video frames from the resolution reducing circuit, when a desired frame rate for the output video stream is different than a frame rate of the input video stream, a depth reduction circuit coupled to the frame reducing circuit configured to reduce bit depth of the plurality of video frames from the frame reducing circuit, when a desired bit depth for the output video stream is different than a bit depth of the input video stream, and a rate reduction circuit coupled to the depth reduction circuit, configured to scale the plurality of video frames from the depth reduction circuit, in response to a desired bit rate for the output video stream, and an encoder coupled to the rate reduction circuit, configured to encode the plurality of video frames from the rate reduction circuit into the output video stream is also contemplated.

System for transforming streaming video data

According to one embodiment, a computer program product for a system including a processor includes a tangible memory including code that directs the processor to determine an output resolution for an output stream of data, code that directs the processor to determine an output frame rate for the output stream of data, code that directs the processor to determine an output color depth for the output stream of data, code that directs the processor to retrieve a first frame of data, a second frame of data, and a third frame of data from an input stream of data, the input stream of data having an input resolution, an input frame rate, and an input color depth, code that directs the processor to subsample the first frame of data, the second frame of data, and the third frame of data to respectively form a first subsampled frame of data, a second subsampled frame of data, and a third subsampled frame of data, when the output resolution is lower than the input resolution are also included, code that directs the processor to remove the second subsampled frame of data, when the output frame rate is lower than the input frame rate, code that directs the processor to reduce color depth for the first subsampled frame of data and the second subsampled frame of data to respectively form a first reduced frame of data and a second reduced frame of data, when the output color depth is smaller than the input color depth, and code that directs the processor to convert the first reduced frame of data and the second reduced frame of data into the output stream of data.

Computer program product for transforming streaming video data

A video encoder/decoder includes a vector pipeline unit and is configured only once by a processor to encode/decode data in accordance with any one of the JPEG, MPEG1, MPEG2 or MPEG4, H.261 or H.263 compression standards. The configuration data is stored in a configuration register of the video encoder/decoder. An optional ROM stores the configuration data for subsequent reading and loading&#x2014;by the processor&#x2014;into the configuration register. The vector pipeline unit includes: a run-length decoder, a binary arithmetic logic unit, a binary multiplier/divider, an accumulator, a barrel shifter, a round/modify unit, a saturate logic unit, a status register and a run-length encoder. Each component of the vector pipeline unit is optionally enabled or disabled. By disabling one or more components of the vector pipeline unit the power consumed by the encoder/decoder is reduced. The vector pipeline, after being configured continuously encodes/decodes vectors of data according to the configured standard, without requiring any additional configuration or software programming. The status register gathers statistical data on the saturated data and supplies the statistical data to the processor, thereby, further improving the performance of the video encode/decoder. The video encoder/decoder encodes/decodes data based on any other compression standard with additional configuration or software programming.

Processor architecture for compression and decompression of video and images

A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.

Error recovery of corrupted MPEG-4 bitstreams using fuzzy decoding of start codes and resync markers

Error detection is added to a motion-picture-experts group (MPEG) decoder by checking each 8&times;8-pixel block for constraints. The constraints are added during compression by adjusting discrete cosine transform (DCT) coefficients in the block to meet a constraint. When the decoder determines that the constraint is not met by the DCT coefficients, an error is signaled for that block. The error can then be concealed using pixels from another frame or block. In one embodiment, the constraint is that the last two non-zero coefficients have the same magnitude. The constraint is added during compression after quantization but before variable-length coding by averaging the magnitudes and using the average magnitude for the last two non-zero coefficients. This minimizes visible distortion caused by the constraints and reduces computations.

Constrained discrete-cosine-transform coefficients for better error detection in a corrupted MPEG-4 bitstreams

An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers, a shift register coupled to the first selector and to the second selector circuit, the shift register configured to receive the data words from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data words, the portion of the data words determined by the pointer, and a decoder coupled to the shift register, the decoder configured to receive the portion of the data words, and configured to output decoded data in response to the portion of the data words.

Growing community of inventors

Los Gatos, CA, United States of America

Stephen A Molloy