Texas Instruments Corporation

Stephen A Keller

Rajiv R Shah

Michael C Smayling

Taylor R Efland

Douglas P Verret

Charles E Williams

Quang X Mai

Abnash C Sachdeva

Martha S Adams

Piper A Spry

Ralph G Harper

Satwinder S Malhi

Douglas Ticknor Grider

Brian Keith Kirkpatrick

Brian Edward Hornung

Byron Joseph Palla

Michael LeRoy Huber

Timothy G Nagel

Phat Xuan Mai

A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

Method for stripping one or more layers from a semiconductor wafer

An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric layer exposing, and not overlapping, the bottom plate, a capacitor dielectric layer covering sidewalls and a bottom of the capacitor opening, a top plate covering the capacitor dielectric layer in the capacitor opening, and a capacitor planarizing dielectric layer covering the capacitor top plate in the capacitor opening. A top surface of the capacitor planarizing dielectric layer and a top edge of the capacitor top plate are substantially coplanar. The top plate does not extend laterally beyond the capacitor opening. A method of forming the integrated circuit the high precision capacitor is also disclosed.

Single pattern high precision capacitor

A method for erasing a non-volatile memory array (18) includes elevating the temperature of the memory array (18) during a ramp-up period. The memory array (18) is irradiated with ultraviolet light at an elevated temperature during an erase period. The temperature of the memory array (18) is incrementally decreased during a ramp-down period.

Method for erasing a non-volatile memory array

A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).

Method of forming improved thick plated copper interconnect and

A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The barrier member (88) may be disposed between the bondable member (86) and the copper lead (50).

Thick plated interconnect and associated auxillary interconnect

A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate at which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide. Additionally disclosed are techniques for forming contacts (139) to the Schottky diode (115) and other integrated circuit structures (107,108) at temperatures below those that would damage the Schottky diode (115).

Platinum silicide Schottky diodes in a titanium-silicided CMOS-based

A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide. Additionally disclosed are techniques for forming contacts (139) to the Schottky diode (115) and other integrated circuit structures (107,108) at temperatures below those that would damage the Schottky diode (115).

Integrated circuit including a FET device and Schottky diode

A method for providing programmable devices in which an insulation layer, such as an oxide (20), TEOS, or the like, is formed during a BiCMOS integrated circuit fabrication process includes forming a first conductor fuse layer (22), for example of TiW or the like, on the insulation layer (20). The fuse layer (22) may then be patterned, and a second insulation layer (23) formed over it. Alternatively, the fuse layer (53) may be left unpatterned and one or more conductor layers (35,36) may be formed over the fuse layer (53). The conductor layer (35,36) is patterned, and the fuse layer (53) thereafter patterned using the conductor layer (35,36) as an etch mask. In either case, contact holes (26) are formed in the insulation layer (20) to regions (14,15) to which contact is desired under the insulation layer (20). Contact conductors (28), such as of tungsten or the like, are formed in the contact holes (26) to contact the fuse (34), contact layers ( 22), or regions (14,15) under the insulation layer (20), as needed.

Method for forming TiW fuses in high performance BiCMOS process

An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Method for forming gigaohm load for BiCMOS process

A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which extends from the D-well region 20 to a first side of the field oxide region 24. A first n doped source/drain region 16 is formed in the D-well region 20 and is spaced from the field oxide region 24. Also, a second n doped source/drain region 18 formed in the silicon layer 14 on a second side of the field oxide region 24. A gate region 26 is formed over the surface of the silicon layer 14 and over a portion of the first source/drain region 16, the D-well region 20, and a portion of the field oxide region 24.

Method of fabricating lateral DMOS structure

A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).

Method of forming high voltage bipolar transistor for a BICMOS

Gigaohm load resistor for BICMOS process

A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Merged bipolar and complementary metal oxide semiconductor transistor

A method for forming CVD tungsten contacts in a planarized semiconductor body. The method utilizes aluminum as an etch mask and etch stop to prevent etching of underlying layers during contact formation.

Aluminum contact etch mask and etchstop for tungsten etchback

Metal interconnects and method for forming same such that an intermediately formed aluminum layer provides an etch stop and etch mask during the tungsten etch back. The method may be used to form tungsten contacts without requiring pre-metal planarization of the semiconductor body.

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Sugarland, TX, United States of America

Stephen A Keller