Fujitsu Corporation

Fujitsu Network Communications, Inc.

Other

Telica, Inc.

Data General Corporation

Stephen A Caldara

Thomas A Manning

Stephen A Hauser

Raymond L Strouble

Robert B McClure

Matthias L Colsman

Richard G Bubenik

Douglas H Hunt

Alan D Sherman

Michael E Gaddis

Michael Sluyski

Sean Garcen

Salvatore Faletra

Louis A Lemone

Edward Gershenson

Mark C Lippitt

David N Peck

John R McDaniel

John Hutchins

William A Braun

James M Meredith

Stephen R Veit

Kenneth S Goekjian

John St Amand

Micheal A Sluyski

Edward N Kittlitz

John E Shur

Donald J Barbarits

George Giordano

A system and method of switching information in a time division multiplexed (TDM) communications network are described. The TDM time slots correspond to channels of circuit information. A circuit interface receives information from the TDM communication network, extracts circuit data therefrom, and provides the extracted circuit data on an internal bus. It also receives circuit data from an internal bus and transmits the data received from the internal bus on to the TDM communications network. A switching fabric receives packets having a header and a payload in which the header includes information identifying a destination for the packet and in which the fabric transmits a received packet in accordance with the destination identification in the packet header. Adaptation logic, in response to the circuit interface, packs information from multiple circuits into a payload of a packet and schedules the delivery of such a packet to the fabric. The adaptation logic receives packets from the switching fabric; and merges circuit data from multiple packets onto an identified channel.

Switching system and method having low, deterministic latency

A system for indicating and determining a master unit from a plurality of logic units is described. The system includes a first logic unit configured to output a first obey signal and receive a first input signal, and a second logic unit configured to output a second obey signal and receive a second input signal. At least one of the first obey signal and the second obey signal is clocked, and a phase relationship of the second obey signal relative to the first obey signal is controllable by the first and second input signals. The system also includes a mastership determination logic unit configured to monitor the first and second obey signals. The mastership determination logic unit is configured to indicate that the first logic unit is the master unit when only the first obey signal is being clocked and to indicate that the second logic unit is the master unit when only the second obey signal is being clocked. The mastership determination logic unit is also configured to indicate that the first logic unit is the master unit when the first and second signals are being clocked in-phase and to indicate that the second logic unit is the master unit when the first and second signals are being clocked out-of-phase. A method of similar features is also describe.

Fault tolerant mastership system and method

A chassis, in the form of a midplane design holds equipment that provides communication services. The midplane design enables cables to be attached to modules secured to the back of the midplane. The rear modules have a minimum of circuitry so as to render them the least likely to fail. The front modules house the majority of the electronics. The rear modules can route the interface signals to a card in the adjacent front slot, directly through the midplane.

Midplane apparatus

A system and method for monitoring and maintaining a plurality of modules are described. Each module of the plurality of modules includes at least one link slave device, and a link controller is connected to link slave devices via a plurality of individual serial, bidirectional connections. The link slave devices and the link controller include protocol logic for communication according to a bidirectional protocol. At predefined time segments and predefined periodicity, the link slave devices drive the corresponding bidirectional link to the controller to provider maintenance information to the controller. At other predefined time segments, the controller drives the bidirectional link to issue commands to the link slave devices. The link slave devices and the link controller include protocol logic for communicating according to a protocol in which all slave devices communicate to the link controller at substantially the same period of time so that the latency for collecting information from the slave devices is independent of the number of such devices.

Maintenance link system and method

An Asynchronous Transfer Mode switch and method which facilitate priority arbitration of point-to-point and point-to-multipoint transmission are disclosed. To execute point-to-multipoint operation a bandwidth arbiter maintains a first list of connections and bit vectors indicating designated destination ports. The list maintained by the bandwidth arbiter is then compared to an unassigned output port bit vector to determine matches therebetween at which point-to-multipoint transmission may be made by utilizing instantaneously unused bandwidth within the switch. To execute point-to-point operation each input port maintains a list of connections associated with each output port, and those lists are used in conjunction with output port request information per input port in the bandwidth arbiter to match requests to the unassigned output port bit vector. The bandwidth arbiter may also assign priority to connections in the list.

Priority arbitration for point-to-point and multipoint transmission

An asynchronous transfer mode (ATM) based service consolidation switch ( ) includes an input/output module ( ) having a to-switch port (TSPP) processor ( ) and a from-switch port processor (FSPP) ( ). The TSPP ( ) and the FSPP ( ) communicate with a bandwidth arbiter ( ), multipoint topology controllers ( ), and a data crossbar ( ) on a switch control module ( ). The TSPP ( ) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP ( ). Multipoint topology controllers ( ) performs translations for internal switch flow control through interactions between the TSPPs ( ), FSPPs ( ), and the bandwidth arbiter ( ). The bandwidth arbiter ( ) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs ( ) to FSPPs ( ) over the data crossbar ( ).

Asynchronous transfer mode based service consolidation switch

An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Data encoder/decoder for a high speed serial link

A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining per-connection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Method and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basis

A system (,) is provided for identifying a processing port (,) and a link (,) at which a cell (,) is received. The system (,) includes a logical link table (,) having a plurality of logical link entries (,). Each logical link entry (,), which corresponds to a particular link (,) of a processing port (,) associated with the logical link table (,), specifies a numerical value. The processing port (,) may receive the cell (,) at one of a plurality of links (,). The processing port (,) can convert the cell (,) by replacing a numerical value of an identification field, such as a virtual channel identification field (,), of the cell (,) with the numerical value specified by the logical link entry (,) corresponding to the link (,) at which the cell (,) is received. A switch control module (,), which is connected to the processing port (,), may receive the converted cell (,). The switch control module (,) can identify the link (,) and the processing port (,) at which the cell (,) corresponding to the converted cell (,) was received by referencing a reverse mapping table (,) using the numerical value of the logical link entry (,) in the converted cell (,).

Port and link identification

A constant phase crossbar switch system which avoids phase discontinuities at the outputs of the crossbar switch. The crossbar switch system includes input logic, a crossbar switch, output logic and a phase locked loop. The phase locked loop is used to generate a high speed internal clock from a system clock. High speed serial data streams transmitted at the internal clock frequency are received from corresponding transmitters and are coupled to the input logic. The input logic generates multiple versions of each serial data stream, one of the versions being undelayed and the other versions delayed by some fraction of a bit time. State machines are employed to selects the version of the serial data stream which results in the data stream data window being generally centered with respect to the high speed internal clock. The selected version of the data stream is employed as the active input to the crossbar switch. The selected version of each of the data stream is clocked into an output register which is clocked by the internal clock. The selection of the phase delayed version of the serial data stream in the described manner avoids phase discontinuities upon switching of sourcing transmitters.

Constant phase crossbar switch

A mechanism enabling plural queues in a downstream telecommunications network element to be treated as a single, joint queue for purposes of connection-level flow control. A pointer in at least one queue descriptor points to a queue descriptor in which is maintained a set of shared, joint counters. Other flow control elements are maintained individually with respect to each queue descriptor. This mechanism enables flow control elements associated with a single transmitter queue to flow control plural connections terminating in plural queues associated with a single receiver processor.

Joint flow control mechanism in a telecommunications network

An Asynchronous Transfer Mode switch and method which facilitate point-to-multipoint transmission are disclosed. Each input port within the switch includes a switch allocation table ('SAT') which manages bandwidth allocation and delay. Each SAT includes a plurality of sequentially ordered cell time slots, a subqueue and a synchronized pointer which is directed to one of the slots such that at any given point in time each of the pointers is directed to the same slot location in the respective SAT with which the pointer is associated. To execute point-to-multipoint operation where output port conflicts are present the switch transmits copies of the cell to the output ports at different points in time. More particularly, the switch transmits copies of the cell to available output ports, and tracks such transmission for managing future transmission to unserviced output ports. To track transmission the switch includes a map and scoreboard. The subqueues are used to index into a table and may be associated with one or more output ports. The map indicates which subqueues, and hence which output ports, are initially eligible to receive a copy of the cell. The scoreboard indicates which subqueues, and hence which output ports, have received a copy of the cell. Tracking is realized by updating the scoreboard when copies of cells are transmitted. Copies of the cell are not sent to already serviced output ports. When each designated subqueue has been service, and hence each associated output port has been serviced, the cell is dequeued.

Point-to-multipoint transmission using subqueues

In a link-level flow controlled system, a method and apparatus providing the ability to partition a buffer resource among multiple prioritized buffer subsets through definition of at least one threshold, the buffer resource being shared by a plurality of connections. Different category of service levels, in terms of delay bounds, are thus enabled. The presently disclosed link-level flow controlled system provides for zero cell loss. The shared buffer resource is divided among N priority pools, defined by N-1 threshold levels, each priority pool attributable to a respective category of service. Link-level counters and registers, disposed in a transmit element, as well as an indication of priority level associated with each connection, are employed in realizing the shared buffer resource.

Growing community of inventors

Sudbury, MA, United States of America

Stephen A Caldara