Altera Corporation

Stephanie T Tran

Guu Lin

Cheng-Hsiung Huang

Chih-Ching Shih

Jim Park

Bruce B Pederson

Jay Schleicher

Brad Vest

Yen-Fu Lin

Irfan Rahim

John C Costello

Shih-Lin S Lee

Mark W Fiester

Chiakang Sung

Andy Louie Lee

Cameron R McClintock

Myron Wai Wong

Brian D Johnson

John Henry Bui

Toan Thanh Nguyen

Jeffrey Tyhach

Mian Z Smith

Chuan-Yung Hung

Pooyan Khoshkhoo

An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.

Flexible data strobe signal bus structure for wirebond and flip-chip packaging

A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.

Apparatus and method for input/output module that optimizes frequency performance in a circuit

Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Flexible macrocell interconnect

Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

Electrostatic discharge protection circuit

Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.

Signal timing for I/O

Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

ESD protection that supports LVDS and OCT

Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.

Techniques for providing increased flexibility to input/output banks with respect to supply voltages

Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

Programmable series on-chip termination impedance and impedance matching

Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.

Charge pump circuits and methods

Improved charge pump circuitry that significantly reduces voltage stress on transistor gate oxides is disclosed. The charge pump circuit according to a preferred embodiment of the present invention includes circuitry that biases the otherwise vulnerable transistors in the charge pump circuit such that the voltage across their gate oxide is reduced. The charge pump of the present invention further provides circuitry to reduce leakage current.

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San Jose, CA, United States of America

Stephanie T Tran