Texas Instruments Corporation

Stephanie Leanne Hilbun

Binghua Hu

Henry Litzmann Edwards

Xiaoju Wu

James Robert Todd

Abbas Ali

Scott William Jessen

Jarvis Benjamin Jacobs

Nital S Patel

Byron Joseph Palla

Steven T Jenkins

Ronald Chin

Clifton E Brooks

Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Drain centered LDMOS transistor with integrated dummy patterns

A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings

An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.

Semiconductor manufacturing optimization by combining small lots into individual carriers

A tuned run-to-run controlled system is disclosed that provides tuned run-to-run control of a system. The system includes a controlled system coupled to a tuned run-to-run controller, which contains a feedback controller coupled to a tuner. Tuned run-to-run controller determines a feedback command based on a nominal gain, a maximum gain, a process error, and a tuning gain.

System and method for self-tuning feedback control of a system

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Garland, TX, United States of America

Stephanie Leanne Hilbun