Nxp B.v.

Koninklijke Philips Corporation N.V.

Entropic Communications, Inc.

Trident Microsystems (far East) Ltd.

Stéphane Mutz

Eric Desmicht

Hugues De Perthuis

Christophe Tison

Thierry Nouvet

Thierry Gourbilleau

Mickaël Guene

The invention relates to a chip for processing a content, comprising at least a microprocessor. Said chip includes an integrated non-volatile programmable memory for storing protection data and protected data, said protection data being intended to be used for authorizing/denying access to said protected data by said microprocessor under execution of a program. The invention allows to protect program and data dedicated to a chip-integrated conditional-access system and to protect features as external connections and downloaded data directly on the chip.

Chip integrated protection means

A functional unit of a device is associated with a secret. Data stored in a memory location of the device is encrypted using the secret. The memory location of the device is accessible to other functional units; but without knowledge of the secret, the stored encrypted data is useless. The sharing of the secret creates a secure path between memory locations and functional units of the device while maintaining a unitary memory architecture. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Establishing a secure memory path in a unitary memory architecture

The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit () including a reconstruction circuit () for reconstructing pictures from decoded data and an external memory () for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller () for controlling data exchange between the processing unit and the external memory, a cache memory () for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit () for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

Video processing device with low memory bandwidth requirements

The invention relates to a secure data processing system including an unscrambling module [DSC] disposed on a dedicated hardware part [HW] of an integrated circuit and intended to unscramble a stream of data [SP] scrambled according to a scrambling key, a module [CM] for calculating an unscrambling key [Kp] disposed on said dedicated hardware part [HW] and intended to manipulate data under the control of a so-called calculation program stored on said dedicated hardware part [HW], a processor [CPU] for in particular controlling the functioning of the unscrambling [DSC] and calculation [CM] modules. Said system also includes a read only memory [SME] disposed on said dedicated hardware part [HW] for storing a secret key [Kp]. Said calculation program includes instructions for prompting said calculation module [CM] to use said secret key [L] and at least one data item [AC[n,p] or Kpc)] coming from outside the secure data processing system, in order to calculate an unscrambling key [Kp]. The unscrambling is enabled only if the unscrambling key [Kp] corresponds to the scrambling key.

Conditional access control

Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:

Method and system for accelerated access to a memory

Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank

A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).

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Caen, France

Stéphane Mutz