Trw Limited

Stephane Mailleau

Barton G Shaler

Gregory P Chapelle

A drum memory controller for controlling random access write and sequential read operations of a drum memory in a communications system. Such drum memory controller ( ) may comprise a drum memory ( ) having a predetermined number of rows and rings forming a plurality of memory locations arranged in a sequential time order; a random access write address generator ( ) which generates write addresses using a respective time tag of incoming data for writing data into memory locations of the drum memory ( ) in a random access time order; and a sequential reader ( ) which generates read addresses at a constant rate for reading out data stored in the memory locations of the drum memory ( ) across each row and then sequencing up in rows in a sequential time order.

Drum memory controller

A memory access system maps a block of data between a time stamp and an addressable memory location in a manner which mimics actual transmission slot timing. The system includes a slot time module, a calculation conversion module, and an addressing module The slot time module determines the time stamp for the block of data, and the calculation conversion module generates a preliminary memory location based on the time stamp and a predetermined conversion factor. The predetermined conversion factor has a preliminary component which can be removed by the addressing module such that an addressable memory location is generated. The calculation conversion module has a base conversion module, a padding module, a left-shift module; and a summation module for constructing the conversion factor and applying the conversion factor to the retrieved time stamp.

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San Diego, CA, United States of America

Stephane Mailleau