Infineon Technologies Ag

Stephane Kirmser

Heinz Mattes

Sebastian Sattler

Simone Borri

M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tlong. The test signal is sampled with N sampled values at a sampling frequency f=1/T. Also, N*T=M*T, where N&#x3e;M. The sampled values are numbered progressively by n, for which 0&#x2266;n &#x2266;N&#x2212;1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tis calculated by K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's iperiod or the last sampled value before a test signal zero crossing during the reference signal's iperiod. Either only rising or only falling zero crossings are taken into account.

Measuring device and method for measuring relative phase shifts of digital signals

A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.

Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device

System for testing a group of functionally independent memories () and for replacing failing memory words of the group of functionally independent memories () by redundant memory words, comprising: redundancy means) including at least one array of redundant memory words () and address registers () connected to at least one array of redundant memory words (); a test means (); a group of first multiplexers () following the test means () and preceding the memories () and the at least one array of redundant memory words (); and a group of second multiplexers () following the memories () and the at least one array of redundant memory words (), wherein each second multiplexer () is connectable to the test means ().

Growing community of inventors

Munich, Germany

Stephane Kirmser