Inphi Corporation

Marvell Asia Pte., Ltd.

Cortina Systems Corporation

Stephane Dallaire

Benjamin P Smith

Brian Wall

Karthik Raviprakash

Praveen Prabha

Luke Wang

Florin Pera

Arash Farhoodfar

Geoffrey O Hatcher

Ray Luan Nguyen

Kenji Suzuki

Travis William Lovitt

Kevin Parker

Lawrence Tse

Simon D Forey

Shawn Lawrence Scouten

Malcolm Stevens

Benjamin Tomas Reyes

Jeff P Kirsten

Basel Alnabulsi

Stephen Alie

An analog front-end (AFE) device includes a sampler array, differential source follower circuits, and programmable attenuation circuits. The sampler array receives input and clock signals. The sampler array including sampling circuits each sampling and holding the input signal based on one of the clock signals. The differential source follower circuits include respective cross-coupled transistor circuits, which include cross-coupled transistors that adjust gain of the sampling circuits. The programmable attenuation circuits include a voltage-controlled resistor that is connected to a differential output of one of the cross-coupled transistor circuits and adjusts gain of a corresponding one of the sampling circuits. The programmable attenuation circuits further receive outputs of the sampling circuits and control signals, and, based on the control signals, adjust the gain for ones of the sampling circuits independently of other ones of the sampling circuits to compensate for gain mismatch between outputs of the sampling circuits.

Method and device for high bandwidth receiver for high baud-rate communications

Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

Hybrid analog/digital equalizer architecture for high-speed receiver

A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.

Variable gain amplifier including impedance ladder circuit with exponentially dependent degeneration resistance

An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.

The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.

Systems and methods for linear variable gain amplifier

Split cascode circuits include multiple cascode paths coupled between voltage supply rails. Each cascode path includes a pair of controllable switches. A feedback path is provided for at least one of the cascode circuit paths. An active load circuit may also have a split cascode structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascode circuits.

Split cascode circuits and related communication receiver architectures

An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.

Apparatus and method for recovering data at an optical receiver with automatic tuning

Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

Clock timing skew may occur during operation of a time-interleaved receiver. It would be beneficial to try to determine if there is timing skew, and if there is, then address it, such as by reducing or eliminating some or all of the timing skew. Embodiments are described herein that may achieve this. In one embodiment, a method includes generating at least two clocks having the same frequency but a different phase. Intersymbol interference (ISI) values are then determined, one for each of the clocks, by: for each clock, sampling a signal using the clock and determining a value representing ISI based on the sampled signal. A clock phase of at least one of the clocks is adjusted in response to at least one of the ISI values being different from a reference ISI value.

System and method for adjusting clock phases in a time-interleaved receiver

Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.

Circuit and method for performing adaption on all receiver branches

Circuit and method for performing adaptation on all receiver branches

A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.

Integrated jitter compliant low bandwidth phase locked loops

According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.

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Gatineau, Canada

Stephane Dallaire